The SCEAS System
Navigation Menu

Search the dblp DataBase


Tadeusz Luba: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Grzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba
    Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:99-104 [Conf]
  2. Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
    NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:248-254 [Conf]
  3. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
    An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:104-111 [Conf]
  4. Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
    Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:460-466 [Conf]
  5. Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, Vlad P. Shmerko, Joanna Kolodziejczyk
    Application of Design Style in Evolutionary Multi-Level Networks Synthesis. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1156-1163 [Conf]
  6. Mariusz Rawski, Lech Józwiak, Tadeusz Luba
    The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1086-1093 [Conf]
  7. Mariusz Rawski, Lech Józwiak, Tadeusz Luba
    Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1094-1101 [Conf]
  8. Mariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki
    Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10008-10015 [Conf]
  9. Rafal Rzechowski, Tadeusz Luba, Lech Józwiak
    Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1368-1375 [Conf]
  10. Piotr Sapiecha, Henry Selvaraj, Jaroslaw Stanczak, Krzysztof Sep, Tadeusz Luba
    A Hybrid Approach to a Classification Problem. [Citation Graph (0, 0)][DBLP]
    Intelligent Information Systems, 2004, pp:99-106 [Conf]
  11. Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
    Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:287-292 [Conf]
  12. Tadeusz Luba
    Decomposition of Multiple-Valued Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:256-0 [Conf]
  13. Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, M. Opoka, Vlad P. Shmerko
    Evolutionary Multi-Level Network Synthesis in Given Design Style. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:253-258 [Conf]
  14. Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
    Decomposition of Multiple-Valued Relations . [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:13-18 [Conf]
  15. Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
    FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    ITCC, 2002, pp:355-360 [Conf]
  16. Henry Selvaraj, Pawel Tomaszewicz, Mariusz Rawski, Tadeusz Luba
    Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2005, pp:22-27 [Conf]
  17. Tadeusz Luba, Robert Lasocki, Janusz Rybnik
    An Implementation of Decomposition Algorithm and its Application in Information System Analysis and Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    RSKD, 1993, pp:458-465 [Conf]
  18. Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba
    Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:388-393 [Conf]
  19. Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
    Functional Decomposition and Its Applications in Machine Learning and Neural Networks. [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Intelligence and Applications, 2001, v:1, n:3, pp:259-271 [Journal]
  20. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
    An application of functional decomposition in ROM-based FSM implementation in FPGA devices. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:424-434 [Journal]

  21. Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. [Citation Graph (, )][DBLP]

  22. Decomposing Pattern Matching Circuit. [Citation Graph (, )][DBLP]

  23. Logic synthesis method for FPGAs with embedded memory blocks. [Citation Graph (, )][DBLP]

  24. Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms. [Citation Graph (, )][DBLP]

  25. Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions. [Citation Graph (, )][DBLP]

  26. New Fastest Linearly Independent Transforms over GF(3). [Citation Graph (, )][DBLP]

  27. Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure. [Citation Graph (, )][DBLP]

Search in 0.003secs, Finished in 0.004secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002