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Zdenek Kotásek :
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Lukás Sekanina , Lukás Starecek , Zdenek Kotásek Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. [Citation Graph (0, 0)][DBLP ] DDECS, 2006, pp:85-86 [Conf ] Tomas Pecenka , Zdenek Kotásek , Lukás Sekanina FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. [Citation Graph (0, 0)][DBLP ] DDECS, 2006, pp:285-289 [Conf ] Zdenek Kotásek , Daniel Mika , Josef Strnadel Test scheduling for embedded systems. [Citation Graph (0, 0)][DBLP ] DSD, 2003, pp:463-467 [Conf ] Josef Strnadel , Zdenek Kotásek Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. [Citation Graph (0, 0)][DBLP ] DSD, 2005, pp:420-427 [Conf ] Josef Strnadel , Zdenek Kotásek Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. [Citation Graph (0, 0)][DBLP ] DSD, 2002, pp:166-173 [Conf ] Tomas Pecenka , Josef Strnadel , Zdenek Kotásek , Lukás Sekanina Testability Estimation Based on Controllability and Observability Parameters. [Citation Graph (0, 0)][DBLP ] DSD, 2006, pp:504-514 [Conf ] Josef Strnadel , Zdenek Kotásek SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. [Citation Graph (0, 0)][DBLP ] ECBS, 2006, pp:497-498 [Conf ] Tomas Pecenka , Zdenek Kotásek , Lukás Sekanina , Josef Strnadel Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. [Citation Graph (0, 0)][DBLP ] Evolvable Hardware, 2005, pp:51-58 [Conf ] Zdenek Kotásek , F. Zboril RT level testability analysis to reduce test application time. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1997, pp:104-0 [Conf ] Lukás Sekanina , Lukás Starecek , Zbysek Gajda , Zdenek Kotásek Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. [Citation Graph (0, 0)][DBLP ] AHS, 2006, pp:186-193 [Conf ] J. Blatný , Zdenek Kotásek I-Path Analysis. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 1995, v:14, n:5, pp:- [Journal ] J. Blatný , Zdenek Kotásek , Jan Hlavicka RT Level Test Scheduling. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 1997, v:16, n:1, pp:- [Journal ] Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. [Citation Graph (, )][DBLP ] Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. [Citation Graph (, )][DBLP ] Power Conscious RTL Test Scheduling. [Citation Graph (, )][DBLP ] Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. [Citation Graph (, )][DBLP ] Online Protocol Testing for FPGA Based Fault Tolerant Systems. [Citation Graph (, )][DBLP ] Digital Systems Architectures Based on On-line Checkers. [Citation Graph (, )][DBLP ] High Availability Fault Tolerant Architectures Implemented into FPGAs. [Citation Graph (, )][DBLP ] Preface. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.005secs