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Zdenek Kotásek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
    Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:85-86 [Conf]
  2. Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
    FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:285-289 [Conf]
  3. Zdenek Kotásek, Daniel Mika, Josef Strnadel
    Test scheduling for embedded systems. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:463-467 [Conf]
  4. Josef Strnadel, Zdenek Kotásek
    Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:420-427 [Conf]
  5. Josef Strnadel, Zdenek Kotásek
    Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:166-173 [Conf]
  6. Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
    Testability Estimation Based on Controllability and Observability Parameters. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:504-514 [Conf]
  7. Josef Strnadel, Zdenek Kotásek
    SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. [Citation Graph (0, 0)][DBLP]
    ECBS, 2006, pp:497-498 [Conf]
  8. Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
    Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2005, pp:51-58 [Conf]
  9. Zdenek Kotásek, F. Zboril
    RT level testability analysis to reduce test application time. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:104-0 [Conf]
  10. Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
    Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:186-193 [Conf]
  11. J. Blatný, Zdenek Kotásek
    I-Path Analysis. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 1995, v:14, n:5, pp:- [Journal]
  12. J. Blatný, Zdenek Kotásek, Jan Hlavicka
    RT Level Test Scheduling. [Citation Graph (0, 0)][DBLP]
    Computers and Artificial Intelligence, 1997, v:16, n:1, pp:- [Journal]

  13. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. [Citation Graph (, )][DBLP]

  14. Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. [Citation Graph (, )][DBLP]

  15. Power Conscious RTL Test Scheduling. [Citation Graph (, )][DBLP]

  16. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. [Citation Graph (, )][DBLP]

  17. Online Protocol Testing for FPGA Based Fault Tolerant Systems. [Citation Graph (, )][DBLP]

  18. Digital Systems Architectures Based on On-line Checkers. [Citation Graph (, )][DBLP]

  19. High Availability Fault Tolerant Architectures Implemented into FPGAs. [Citation Graph (, )][DBLP]

  20. Preface. [Citation Graph (, )][DBLP]

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