The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Hana Kubatova: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Petr Fiser, Hana Kubatova
    Multiple-Vector Column-Matching BIST Design Method. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:268-273 [Conf]
  2. Pavel Kubalík, Radek Dobias, Hana Kubatova
    Dependability Computation for Fault Tolerant Reconfigurable Duplex System. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:100-102 [Conf]
  3. Pavel Kubalík, Jirí Kvasnicka, Hana Kubatova
    Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:357-360 [Conf]
  4. Radek Dobias, Hana Kubatova
    FPGA Based Design of the Railway's Interlocking Equipments. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:467-473 [Conf]
  5. Peter Filter, Hana Kubatova
    Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:56-63 [Conf]
  6. Petr Fiser, Jan Hlavicka, Hana Kubatova
    FC-Min: A Fast Multi-Output Boolean Minimizer. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:451-454 [Conf]
  7. Petr Fiser, Hana Kubatova
    Boolean Minimizer FC-Min: Coverage Finding Process. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:152-159 [Conf]
  8. Petr Fiser, Hana Kubatova
    Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:369-376 [Conf]
  9. Pavel Kubalík, Radek Dobias, Hana Kubatova
    Dependable Design for FPGA Based on Duplex System and Reconfiguration. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:139-145 [Conf]
  10. Petr Fiser, Hana Kubatova
    Survey of the Algorithms in the Column-Matching BIST Method. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:181- [Conf]
  11. Pavel Kubalík, Petr Fiser, Hana Kubatova
    Fault Tolerant System Design Method Based on Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:185-186 [Conf]
  12. Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:262-265 [Journal]

  13. Experimental SEU Impact on Digital Design Implemented in FPGAs. [Citation Graph (, )][DBLP]


  14. An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. [Citation Graph (, )][DBLP]


  15. Dependability Evaluation of Real Railway Interlocking Device. [Citation Graph (, )][DBLP]


  16. Reliable Railway Station System Based on Regular Structure Implemented in FPGA. [Citation Graph (, )][DBLP]


Search in 0.204secs, Finished in 0.205secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002