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Stanislaw Deniziak: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Radoslaw Czarnecki, Stanislaw Deniziak
    Resource Constrained Co-synthesis of Self-reconfigurable SOPCs. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:49-54 [Conf]
  2. Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha
    An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:443-446 [Conf]
  3. Stanislaw Deniziak, Krzysztof Sapiecha
    High Level Testbench Generation for VHDL Models. [Citation Graph (0, 0)][DBLP]
    ECBS, 1999, pp:146-151 [Conf]
  4. Joanna Strug, Stanislaw Deniziak, Krzysztof Sapiecha
    Validation of Reactive Embedded Systems against Temporal Requirements. [Citation Graph (0, 0)][DBLP]
    ECBS, 2004, pp:152-160 [Conf]
  5. Stanislaw Deniziak, Krzysztof Sapiecha
    Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:201-204 [Conf]
  6. Stanislaw Deniziak, Krzysztof Sapiecha
    Developing a High-Level Fault Simulation Standard. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:5, pp:89-90 [Journal]

  7. A symbolic RTL synthesis for LUT-based FPGAs. [Citation Graph (, )][DBLP]

  8. Contention-avoiding custom topology generation for network-on-chip. [Citation Graph (, )][DBLP]

  9. An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs. [Citation Graph (, )][DBLP]

  10. Rapid Prototyping of NoC Architectures from a SystemC Specification. [Citation Graph (, )][DBLP]

  11. An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. [Citation Graph (, )][DBLP]

  12. Hardware/Software Co-synthesis of Distributed Embedded Systems Using Genetic Programming. [Citation Graph (, )][DBLP]

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