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Juan J. Rodríguez-Andina: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:295-300 [Conf]
  2. Lucía Costas, Juan J. Rodríguez-Andina
    Characterization of Wavelet-Based Image Coding Systems for Algorithmic Fault Detection. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:64-71 [Conf]
  3. Miguel Pereira, Enrique Soto, Juan J. Rodríguez-Andina, F. Javier González-Castaño
    High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:282-288 [Conf]
  4. Juan J. Rodríguez-Andina, J. Alvarez, Enrique Mandado
    Design of Safety Systems Using Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:341-343 [Conf]
  5. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:257-262 [Conf]
  6. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  7. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:207-212 [Conf]
  8. Santiago Fernández-Gomez, Juan J. Rodríguez-Andina, Enrique Mandado
    Concurrent error detection in block ciphers [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:979-984 [Conf]
  9. Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina
    FPGA Implementation of High-Performance PHM / DPHM Schedulers. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  10. Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, J. P. Teixeira
    On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:167-172 [Conf]

  11. Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. [Citation Graph (, )][DBLP]


  12. Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. [Citation Graph (, )][DBLP]


  13. Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. [Citation Graph (, )][DBLP]


  14. Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. [Citation Graph (, )][DBLP]


  15. Signal Integrity Enhancement in Digital Circuits. [Citation Graph (, )][DBLP]


  16. Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems. [Citation Graph (, )][DBLP]


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