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Yngvar Berg: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg
    Self-refreshing Multiple Valued Memory. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:94-96 [Conf]
  2. Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg
    Multiple Valued Counter. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:247-249 [Conf]
  3. Yngvar Berg, Jon-Erik Ruth, Tor Sverre Lande
    Scalable Mean Rate Signal Encoding Analog Neural Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1668-1671 [Conf]
  4. Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin
    Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:193-196 [Conf]
  5. Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin
    Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:345-348 [Conf]
  6. Øivind Næss, Espen A. Olsen, Yngvar Berg, Tor Sverre Lande
    A low voltage second order biquad using pseudo floating-gate transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:125-128 [Conf]
  7. Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
    Extreme low-voltage floating-gate CMOS transconductance amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:37-40 [Conf]
  8. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Floating-gate CMOS differential analog inverter for ultra low-voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:9-12 [Conf]
  9. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:838-841 [Conf]
  10. Yngvar Berg, Tor Sverre Lande
    Area efficient circuit tuning with floating-gate techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:396-399 [Conf]
  11. Yngvar Berg, Tor Sverre Lande
    Tunable current mirrors for ultra low voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:17-20 [Conf]
  12. Henning Gundersen, Yngvar Berg
    Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:857-860 [Conf]
  13. Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin
    A novel floating-gate multiple-valued CMOS full-adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:877-880 [Conf]
  14. Øivind Næss, Yngvar Berg
    Tunable floating-gate low-voltage transconductor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:663-666 [Conf]
  15. Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande
    A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:397-400 [Conf]
  16. Mats Høvin, Dag T. Wisland, Yngvar Berg, J. T. Marienborg, Tor Sverre Lande
    Delta-sigma modulation in single neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:617-620 [Conf]
  17. Johannes Goplen Lomsdalen, Yngvar Berg, Renè Jensen
    A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency tripler. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:501-504 [Conf]
  18. Yngvar Berg, Øivind Næss, Snorre Aunet, R. Jensen, Mats Høvin
    Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:385-388 [Conf]
  19. Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari
    Basic Multiple-Valued Functions Using Recharge CMOS Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:346-351 [Conf]
  20. Henning Gundersen, Yngvar Berg
    A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:18- [Conf]
  21. Henning Gundersen, Renè Jensen, Yngvar Berg
    A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:54-58 [Conf]
  22. Omid Mirmotahari, Yngvar Berg
    A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:227-0 [Conf]
  23. Omid Mirmotahari, Yngvar Berg
    A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:135-138 [Conf]
  24. Omid Mirmotahari, Yngvar Berg
    A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:210-213 [Conf]
  25. Snorre Aunet, Yngvar Berg
    UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:57-64 [Conf]
  26. Henning Gundersen, Yngvar Berg
    A novel ternary more, less and equality circuit using recharged semi-floating gate devices. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Øivind Næss, Yngvar Berg
    Switched pseudo floating-gate reconfigurable linear threshold elements. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Yngvar Berg, Omid Mirmotahari, Snorre Aunet
    Pseudo Floating-Gate Inverter with Feedback Control. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:272-277 [Conf]

  29. Low voltage precharge CMOS logic. [Citation Graph (, )][DBLP]

  30. Ultra low-voltage switched current mirror. [Citation Graph (, )][DBLP]

  31. Low Voltage Design against Power Analysis Attacks. [Citation Graph (, )][DBLP]

  32. Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. [Citation Graph (, )][DBLP]

  33. Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. [Citation Graph (, )][DBLP]

  34. Fault Tolerant CMOS Logic Using Ternary Gates. [Citation Graph (, )][DBLP]

  35. Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices. [Citation Graph (, )][DBLP]

  36. Low Voltage Semi Floating-Gate Binary to Multiple-Value and Multiple-Value to Binary Converters. [Citation Graph (, )][DBLP]

  37. New SRAM design using body bias technique for ultra low power applications. [Citation Graph (, )][DBLP]

  38. High Speed Ultra Low Voltage CMOS inverter. [Citation Graph (, )][DBLP]

  39. Ultra Low Voltage High Speed Differential CMOS Inverter. [Citation Graph (, )][DBLP]

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