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Mohammad Hossein Neishaburi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi
    A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:247-250 [Conf]
  2. Masoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, M. Riazati, Ali Afzali-Kusha, Simak Mohammadi
    Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:546-550 [Conf]
  3. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
    A UML Based System Level Failure Rate Assessment Technique for SoC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:243-248 [Conf]
  4. Mohammad Hossein Neishaburi, Masoud Daneshtalab, Majid Nabi, Simak Mohammadi
    System Level Voltage Scheduling Technique Using UML-RT Model. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:500-505 [Conf]
  5. Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari
    Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:528-534 [Conf]
  6. Alireza Aminlou, Maryam Homayouni, Mohammad Hossein Neishaburi, Siamak Mohammadi
    A Superior Low Complexity Rate Control Algorithm. [Citation Graph (0, 0)][DBLP]
    AICCSA, 2007, pp:726-729 [Conf]
  7. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
    Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:205-206 [Conf]

  8. An efficent dynamic multicast routing protocol for distributing traffic in NOCs. [Citation Graph (, )][DBLP]


  9. Enabling efficient post-silicon debug by clustering of hardware-assertions. [Citation Graph (, )][DBLP]


  10. Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. [Citation Graph (, )][DBLP]


  11. On-Chip Verification of NoCs Using Assertion Processors. [Citation Graph (, )][DBLP]


  12. Reliability aware NoC router architecture using input channel buffer sharing. [Citation Graph (, )][DBLP]


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