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Sergio D'Angelo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi
    A Fault-Tolerant FPGA-based Multi-Stage Interconnection Network for Space Applications. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:302-308 [Conf]
  2. Sergio D'Angelo, Cecilia Metra, S. Pastore, A. Pogutz, Giacomo R. Sechi
    Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:233-240 [Conf]
  3. Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:330-338 [Conf]
  4. Monica Alderighi, Fabio Casini, Sergio D'Angelo, M. Mancini, A. Marmo, S. Pastore, Giacomo R. Sechi
    A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:71-78 [Conf]
  5. Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi
    A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:191-199 [Conf]
  6. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:155-163 [Conf]
  7. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri
    Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:274-0 [Conf]
  8. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi
    EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:259-266 [Conf]
  9. Sergio D'Angelo, Lauro Mantoani, Riccardo P. G. Mazzei, Stefania Russo, Giacomo R. Sechi
    Modular Design of Communication Node Prototypes. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:170-175 [Conf]
  10. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, F. d'Ovidio
    Experimenting Genetic Algorithms for Training a Neural Network Prototype for Photon Event Identification. [Citation Graph (0, 0)][DBLP]
    HICSS (3), 1998, pp:283-291 [Conf]
  11. Monica Alderighi, Fabio Casini, Sergio D'Angelo, F. Faure, M. Mancini, S. Pastore, Giacomo R. Sechi, Raoul Velazco
    Radiation test methodology for SRAM-based FPGAs by using THESIC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:162- [Conf]
  12. Monica Alderighi, Sergio D'Angelo, M. Mancini, Giacomo R. Sechi
    A Fault Injection Tool for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:129-0 [Conf]
  13. Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra
    Novel Fault-Tolerant Adder Design for FPGA-Based Systems. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:54-0 [Conf]
  14. Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, Giacomo R. Sechi
    Heavy Ion Effects on Configuration Logic of Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:49-53 [Conf]
  15. Sergio D'Angelo, L. Lisca, A. Proserpio, Giacomo R. Sechi
    Microprogramming in multiprocessor data acquisition system. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:120-133 [Conf]
  16. Sergio D'Angelo, Giacomo R. Sechi
    Definition of elementary arithmetic operations by using ACM. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:160-162 [Conf]

  17. Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform. [Citation Graph (, )][DBLP]


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