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Jan Hlavicka :
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Jan Hlavicka , Petr Fiser Minimization and Partitioning Method Reducing Input Sets. [Citation Graph (0, 0)][DBLP ] DELTA, 2002, pp:434-436 [Conf ] Petr Fiser , Jan Hlavicka On the Use of Mutations in Boolean Minimization. [Citation Graph (0, 0)][DBLP ] DSD, 2001, pp:300-309 [Conf ] Petr Fiser , Jan Hlavicka , Hana Kubatova FC-Min: A Fast Multi-Output Boolean Minimizer. [Citation Graph (0, 0)][DBLP ] DSD, 2003, pp:451-454 [Conf ] Jan Hlavicka , Stanislav Racek C-Sim - The C Language Enhancement for Discrete-Time Simulations. [Citation Graph (0, 0)][DBLP ] DSN, 2002, pp:539- [Conf ] Pavel Herout , Stanislav Racek , Jan Hlavicka Model-Based Dependability Evaluation Method for TTP/C Based Systems. [Citation Graph (0, 0)][DBLP ] EDCC, 2002, pp:271-282 [Conf ] Jan Hlavicka Position Paper. [Citation Graph (0, 0)][DBLP ] EDCC, 1994, pp:411- [Conf ] Jan Hlavicka On the Complexity of System-Level Diagnosis Algorithms. [Citation Graph (0, 0)][DBLP ] EUROCAST, 1991, pp:352-364 [Conf ] Jan Hlavicka , Stanislav Racek , Pavel Smrha Functional Validation of Fault-Tolerant Asynchronous Algorithms. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1996, pp:143-150 [Conf ] Jan Hlavicka , Petr Fiser BOOM - A Heuristic Boolean Minimizer. [Citation Graph (0, 0)][DBLP ] ICCAD, 2001, pp:439-442 [Conf ] Jan Hlavicka Validation and Verification of Hardware and Software (Position Statement). [Citation Graph (0, 0)][DBLP ] IFIP Congress, 1989, pp:343- [Conf ] Astrit Ademaj , Petr Grillinger , Pavel Herout , Jan Hlavicka Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. [Citation Graph (0, 0)][DBLP ] IOLTW, 2002, pp:21-25 [Conf ] J. Blatný , Zdenek Kotásek , Jan Hlavicka RT Level Test Scheduling. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 1997, v:16, n:1, pp:- [Journal ] Khaled Elshafey , Jan Hlavicka Fault-Tolerant FPGA-Based Systems. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 2002, v:21, n:5, pp:- [Journal ] Petr Fiser , Jan Hlavicka BOOM - A Heuristic Boolean Minimizer. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 2003, v:22, n:1, pp:- [Journal ] Stanislav Racek , Pavel Herout , Jan Hlavicka Dependability Evaluation of Time Triggered Architecture Using Simulation. [Citation Graph (0, 0)][DBLP ] Computers and Artificial Intelligence, 2004, v:23, n:1, pp:- [Journal ] Yervant Zorian , Jan Hlavicka Guest Editors' Introduction: East Meets West. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1996, v:13, n:1, pp:5-7 [Journal ] Jan Hlavicka Automatische Belegung von Flachbaugruppen im System PENTA-3. [Citation Graph (0, 0)][DBLP ] Elektronische Rechenanlagen, 1973, v:15, n:1, pp:25-28 [Journal ] Jan Hlavicka , Stanislav Racek , Pavel Herout Evaluation of process controller fault tolerance using simulation. [Citation Graph (0, 0)][DBLP ] Simul. Pr. Theory, 2000, v:7, n:8, pp:769-790 [Journal ] P. Golan , Ondrej Novák , Jan Hlavicka Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1988, v:37, n:4, pp:496-500 [Journal ] Search in 0.002secs, Finished in 0.002secs