The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Giacomo Buonanno: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini
    Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:312-317 [Conf]
  2. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Fault Detection in Sequential Circuits through Functional Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:191-198 [Conf]
  3. Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
    Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:204-211 [Conf]
  4. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A CMOS Fault Tolerant Architecture for Swith-Level Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:10-18 [Conf]
  5. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:223-230 [Conf]
  6. Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto
    How an "Evolving" Fault Model Improves the Behavioral Test Generation. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:124-0 [Conf]
  7. M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto
    Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:654-658 [Conf]
  8. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Functional Fault Models and Gate Level Coverage for Sequential Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:572-575 [Conf]
  9. Paolo Faverio, Donatella Sciuto, Giacomo Buonanno
    Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs. [Citation Graph (0, 0)][DBLP]
    ICEIS (1), 2005, pp:285-292 [Conf]
  10. Giacomo Buonanno, Stefano Gramignoli, Aurelio Ravarini, Marco Tagliavini, Donatella Sciuto
    ICT diffusion and strategic role within Italian SMEs. [Citation Graph (0, 0)][DBLP]
    IRMA Conference, 2000, pp:373-378 [Conf]
  11. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    CMOS Reliability Improvements Through a New Fault Tolerant Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:83-86 [Conf]
  12. Giacomo Buonanno, Fabio Salice, Donatella Sciuto
    Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1924-1927 [Conf]
  13. Giacomo Buonanno, Franco Fummi, Donatella Sciuto
    Functional Testing and Constrained Synthesis of Sequential Architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1523-1526 [Conf]
  14. Giacomo Buonanno, Fabrizio Ferrandi, Donatella Sciuto
    Data Path Testability Analysis Based on BDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2012-2014 [Conf]
  15. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    An Expert Solution to Functional Testability Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    SEKE, 1993, pp:263-265 [Conf]
  16. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A new switching-level approach to multiple-output functions synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:125-129 [Conf]
  17. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    New CMOS Structures for the Synthesis of Dominant Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:367-370 [Conf]
  18. Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami
    A high-level synthesis approach to design of fault-tolerant systems. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:356-363 [Conf]
  19. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    Innovative Structures for CMOS Combinational Gates Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:385-399 [Journal]
  20. Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza
    ALADIN: a multilevel testability analyzer for VLSI system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:157-171 [Journal]

Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002