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Publications of Author

1. N. Devtaprasanna, Sudhakar M. Reddy, A. Gunda, P. Krishnamurthy, Irith Pomeranz
   Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:202-207 [Conf]
   
2. Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda
   Should Illinois-Scan Based Architectures be Centralized or Distributed? [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:406-414 [Conf]
   
3. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
   Test Generation for Open Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   DFT, 2006, pp:41-49 [Conf]
   
4. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
   A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:471-474 [Conf]
   
5. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
   A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. [Citation Graph (0, 0)][DBLP]
   European Test Symposium, 2006, pp:185-192 [Conf]
   
6. 
   Detectability of internal bridging faults in scan chains. [Citation Graph (, )][DBLP]
   
   
7. 
   Systematic Scan Reconfiguration. [Citation Graph (, )][DBLP]
   
   
8. 
   Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. [Citation Graph (, )][DBLP]
   
   
9. 
   Improving the Detectability of Resistive Open Faults in Scan Cells. [Citation Graph (, )][DBLP]
   
   
10. 
    An Enhanced Logic BIST Architecture for Online Testing. [Citation Graph (, )][DBLP]
    
    
11. 
    On the Detectability of Scan Chain Internal Faults — An Industrial Case Study. [Citation Graph (, )][DBLP]