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Renato Stefanelli: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli
    Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:204-211 [Conf]
  2. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A CMOS Fault Tolerant Architecture for Swith-Level Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:10-18 [Conf]
  3. A. Dell'Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson
    System Level Policies for Fault Tolerance Issues in the FERMI Project. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:1-8 [Conf]
  4. F. Distante, Mariagiovanna Sami, Renato Stefanelli
    Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:261-271 [Conf]
  5. Fabio Salice, Mariagiovanna Sami, Renato Stefanelli
    Fault-Tolerant CAM Architectures: A Design Framework. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:233-244 [Conf]
  6. Donatella Sciuto, Cristina Silvano, Renato Stefanelli
    Systematic AUED Codes for Self-Checking Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:183-191 [Conf]
  7. F. Distante, Mariagiovanna Sami, Renato Stefanelli
    Array partitioning to achieve defect tolerance. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:487-491 [Conf]
  8. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    CMOS Reliability Improvements Through a New Fault Tolerant Technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:83-86 [Conf]
  9. Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
    A Technique for Reconfiguring Two Dimensional VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1987, pp:44-53 [Conf]
  10. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    A new switching-level approach to multiple-output functions synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:125-129 [Conf]
  11. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    New CMOS Structures for the Synthesis of Dominant Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:367-370 [Conf]
  12. Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli
    Fault Tolerance Fechniques for Array Structures Used in Supercomputing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1986, v:19, n:2, pp:78-87 [Journal]
  13. Renato Stefanelli, Azriel Rosenfeld
    Some Parallel Thinning Algorithms for Digital Pictures. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1971, v:18, n:2, pp:255-264 [Journal]
  14. Mariagiovanna Sami, Renato Stefanelli
    Compression algorithms that preserve basic topological features in binary-coded patterns. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1973, v:5, n:2, pp:133-147 [Journal]
  15. Renato Stefanelli
    A comment on an investigation into the skeletonization approach of Hilditch. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1986, v:19, n:1, pp:13-14 [Journal]
  16. Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
    Innovative Structures for CMOS Combinational Gates Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:4, pp:385-399 [Journal]
  17. Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli
    An algorithm for functional reconfiguration of fixed-size arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:10, pp:1114-1118 [Journal]
  18. Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli
    Reconfiguration of VLSI arrays by covering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:952-965 [Journal]

  19. Reconfigurable architectures for VLSI processing arrays. [Citation Graph (, )][DBLP]


  20. Multi-parallel convolvers. [Citation Graph (, )][DBLP]


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