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Eiji Fujiwara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Jien-Chung Lo, Eiji Fujiwara
A Probabilistic Measurement for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
DFT, 1993, pp:263-270 [Conf] - Eiji Fujiwara, Masaharu Tanaka
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. [Citation Graph (0, 0)][DBLP]
DFT, 1993, pp:183-190 [Conf] - Masato Kitakami, Hongyuan Chen, Eiji Fujiwara
Evaluations of Burst Error Recovery for VF Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
DFT, 2000, pp:183-191 [Conf] - Haruhiko Kaneko, Eiji Fujiwara
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. [Citation Graph (0, 0)][DBLP]
DFT, 2003, pp:242-249 [Conf] - Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
DFT, 2005, pp:120-130 [Conf] - Kazuteru Namba, Eiji Fujiwara
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. [Citation Graph (0, 0)][DBLP]
DFT, 2001, pp:299-307 [Conf] - Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. [Citation Graph (0, 0)][DBLP]
DFT, 1999, pp:284-292 [Conf] - Ganesan Umanesan, Eiji Fujiwara
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. [Citation Graph (0, 0)][DBLP]
DFT, 2000, pp:192-200 [Conf] - Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. [Citation Graph (0, 0)][DBLP]
DFT, 2006, pp:175-183 [Conf] - Eiji Fujiwara, Mitsuru Hamada
Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems. [Citation Graph (0, 0)][DBLP]
FTCS, 1992, pp:494-501 [Conf] - Eiji Fujiwara, Masato Kitakami
A Class of Error Locating Codes for Byte-Organized Memory Systems. [Citation Graph (0, 0)][DBLP]
FTCS, 1993, pp:110-119 [Conf] - Eiji Fujiwara, Masato Kitakami
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems. [Citation Graph (0, 0)][DBLP]
FTCS, 1995, pp:310-319 [Conf] - Tepparit Ritthongpitak, Masato Kitakami, Eiji Fujiwara
Optimal Two-Level Unequal Error Control Codes for Computer Systems. [Citation Graph (0, 0)][DBLP]
FTCS, 1996, pp:190-199 [Conf] - Haruhiko Kaneko, Mariko Numakami, Eiji Fujiwara
Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method. [Citation Graph (0, 0)][DBLP]
PRDC, 2004, pp:219-226 [Conf] - Ganesan Umanesan, Eiji Fujiwara
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. [Citation Graph (0, 0)][DBLP]
PRDC, 2002, pp:247-256 [Conf] - Eiji Fujiwara, Dhiraj K. Pradhan
Error-Control Coding in Computers. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 1990, v:23, n:7, pp:63-72 [Journal] - Kazuteru Namba, Eiji Fujiwara
A class of systematic m-ary single-symbol error correcting codes. [Citation Graph (0, 0)][DBLP]
Systems and Computers in Japan, 2001, v:32, n:6, pp:21-28 [Journal] - Eiji Fujiwara, Kohji Matsuoka
A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1987, v:36, n:1, pp:86-93 [Journal] - Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1984, v:33, n:6, pp:578-583 [Journal] - Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami
Optimal Two-Level Unequal Error Control Codes for Computer Systems. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1998, v:47, n:12, pp:1313-1325 [Journal] - Mitsuru Hamada, Eiji Fujiwara
A Class of Error Control Codes for Byte Organized Memory Systems —SbEC-(Sb+S)ED Codes—. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1997, v:46, n:1, pp:105-109 [Journal] - Shigeo Kaneda, Eiji Fujiwara
Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1982, v:31, n:7, pp:596-602 [Journal] - Haruhiko Kaneko, Eiji Fujiwara
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2004, v:53, n:2, pp:159-167 [Journal] - Jien-Chung Lo, Eiji Fujiwara
Probability to Achieve TSC Goal. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1996, v:45, n:4, pp:450-460 [Journal] - Ganesan Umanesan, Eiji Fujiwara
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2003, v:52, n:7, pp:835-847 [Journal] - Ganesan Umanesan, Eiji Fujiwara
Parallel Decoding Cyclic Burst Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2005, v:54, n:1, pp:87-92 [Journal] - Eiji Fujiwara, Masato Kitakami
A class of error-correcting codes for byte-organized memory systems. [Citation Graph (0, 0)][DBLP]
IEEE Transactions on Information Theory, 1994, v:40, n:6, pp:1857-1865 [Journal]
Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes. [Citation Graph (, )][DBLP]
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. [Citation Graph (, )][DBLP]
Three-Level Error Control Coding for Dependable Solid-State Drives. [Citation Graph (, )][DBLP]
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