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Antonio Miele: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto
    A model of soft error effects in generic IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:334-342 [Conf]
  2. Cristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante
    Reliable System Co-Design: The FIR Case Study. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:433-441 [Conf]
  3. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  4. Luciano Baresi, Carlo Ghezzi, Antonio Miele, Matteo Miraz, Andrea Naggi, Filippo Pacifici
    Hybrid service-oriented architectures: a case-study in the automotive domain. [Citation Graph (0, 0)][DBLP]
    SEM, 2005, pp:62-68 [Conf]
  5. Cristiana Bolchini, Carlo Curino, Marco Giorgetta, Alessandro Giusti, Antonio Miele, Fabio A. Schreiber, Letizia Tanca
    PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices. [Citation Graph (0, 0)][DBLP]
    SEBD, 2004, pp:166-177 [Conf]

  6. ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration. [Citation Graph (, )][DBLP]


  7. A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. [Citation Graph (, )][DBLP]


  8. TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. [Citation Graph (, )][DBLP]


  9. Design Space Exploration for the Design of Reliable. [Citation Graph (, )][DBLP]


  10. A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems. [Citation Graph (, )][DBLP]


  11. Fault Models and Injection Strategies in SystemC Specifications. [Citation Graph (, )][DBLP]


  12. A methodology for preference-based personalization of contextual data. [Citation Graph (, )][DBLP]


  13. Multi-level fault modeling for transaction-level specifications. [Citation Graph (, )][DBLP]


  14. An integrated flow for the design of hardened circuits on SRAM-based FPGAs. [Citation Graph (, )][DBLP]


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