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Minsu Choi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Repairability Evaluation of Embedded Multiple Region DRAMs. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:428-436 [Conf]
  2. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:419-427 [Conf]
  3. N.-J. Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi
    Regressive Testing for System-on-Chip with Unknown-Good-Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:393-400 [Conf]
  4. Zachary D. Patitz, Nohpill Park, Minsu Choi, Fred J. Meyer
    QCA-Based Majority Gate Design under Radius of Effect-Induced Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:217-228 [Conf]
  5. Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park
    Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:80-88 [Conf]
  6. Shanrui Zhang, Minsu Choi, Nohpill Park
    Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:356-364 [Conf]
  7. Shanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:48-56 [Conf]
  8. Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
    Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:98-106 [Conf]
  9. Minsu Choi, Nohpill Park, Fabrizio Lombardi
    Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  10. Minsu Choi, Nohpill Park
    Teaching Nanotechnology by Introducing Crossbar-Based Architecture and Quantum-Dot Cellular Automata. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:29-30 [Conf]
  11. Minsu Choi, Hardy J. Pottinger, Nohpill Park, Yong-Bin Kim
    Need For Undergraduate And Graduate-Level Education In Testing Of Microelectronic Circuits And Systems. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:121-122 [Conf]
  12. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Optimal Spare Utilization in Repairable and Reliable Memory Cores. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:64-71 [Conf]
  13. Minsu Choi, N.-J. Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    NCA, 2003, pp:341-0 [Conf]
  14. Minsu Choi, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi
    Hardware/Software Co-Reliability of Configurable Digital Systems. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:67-74 [Conf]
  15. Minsu Choi, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi
    Connectivity-Based Multichip Module Repair. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:19-26 [Conf]
  16. Satish K. Bandapati, Scott C. Smith, Minsu Choi
    Design and Characterization of Null Convention Self-Timed Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:26-36 [Journal]
  17. Minsu Choi, Nohpill Park, Vincenzo Piuri, Yong-Bin Kim, Fabrizio Lombardi
    Balanced dual-stage repair for dependable embedded memory cores. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:5, pp:281-285 [Journal]
  18. Bin Liu, Fabrizio Lombardi, Nohpill Park, Minsu Choi
    Testing Layered Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:710-722 [Journal]
  19. Myungsu Choi, Zachary D. Patitz, Byoungjae Jin, Feng Tao, Nohpill Park, Minsu Choi
    Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:551-567 [Journal]

  20. Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture. [Citation Graph (, )][DBLP]

  21. Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. [Citation Graph (, )][DBLP]

  22. Performance assessment of analog circuits with carbon nanotube FET (CNFET). [Citation Graph (, )][DBLP]

  23. Leakage Minimization Technique for Nanoscale CMOS VLSI. [Citation Graph (, )][DBLP]

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