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John M. Emmert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John M. Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici
    On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:445-454 [Conf]
  2. John M. Emmert, Jason A. Cheatham
    On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:149-0 [Conf]
  3. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:303-0 [Conf]
  4. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:361-368 [Conf]
  5. Miron Abramovici, John M. Emmert, Charles E. Stroud
    Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:73-92 [Conf]
  6. John M. Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici
    Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:165-174 [Conf]
  7. John M. Emmert, Dinesh Bhatia
    A Methodology for Fast FPGA Floorplanning. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:47-56 [Conf]
  8. John M. Emmert, Dinesh Bhatia
    Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:141-150 [Conf]
  9. John M. Emmert, Dinesh Bhatia
    Tabu Search: Ultra-Fast Placement for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:81-90 [Conf]
  10. John M. Emmert, Akash Randhar, Dinesh Bhatia
    Fast Floorplanning for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1998, pp:129-138 [Conf]
  11. John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
    Performance Penalty for Fault Tolerance in Roving STARs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:545-554 [Conf]
  12. Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John M. Emmert
    On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:27-33 [Conf]
  13. Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John M. Emmert
    Improving On-Line BIST-Based Diagnosis for Roving STARs. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:31-39 [Conf]
  14. John M. Emmert, Dinesh Bhatia
    Fast timing driven placement using tabu search. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:302-305 [Conf]
  15. Charles E. Stroud, John M. Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic
    Bridging fault extraction from physical design data for manufacturing test development. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:760-769 [Conf]
  16. John M. Emmert, Sandeep Lodha, Dinesh Bhatia
    On Using Tabu Search for Design Automation of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    J. Heuristics, 2003, v:9, n:1, pp:75-90 [Journal]
  17. Jason A. Cheatham, John M. Emmert, Stanley Baumgart
    A survey of fault tolerant methodologies for FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:501-533 [Journal]
  18. Miron Abramovici, Charles E. Stroud, John M. Emmert
    Online BIST and BIST-based diagnosis of FPGA logic blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1284-1294 [Journal]
  19. John M. Emmert, Charles E. Stroud, Miron Abramovici
    Online Fault Tolerance for FPGA Logic Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:216-226 [Journal]

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