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Jason A. Cheatham: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John M. Emmert, Jason A. Cheatham
    On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:149-0 [Conf]
  2. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:303-0 [Conf]
  3. John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
    An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:361-368 [Conf]
  4. John M. Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
    Performance Penalty for Fault Tolerance in Roving STARs. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:545-554 [Conf]
  5. Jason A. Cheatham, John M. Emmert, Stanley Baumgart
    A survey of fault tolerant methodologies for FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:2, pp:501-533 [Journal]

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