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Jayabrata Ghosh-Dastidar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jayabrata Ghosh-Dastidar, Nur A. Touba
    Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:215-220 [Conf]
  2. Jayabrata Ghosh-Dastidar, Nur A. Touba
    A Systematic Approach for Diagnosing Multiple Delay Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:211-216 [Conf]
  3. Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba
    Fault diagnosis in scan-based BIST using both time and space information. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:95-102 [Conf]
  4. Jayabrata Ghosh-Dastidar, Nur A. Touba
    Adaptive Techniques for Improving Delay Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:168-172 [Conf]
  5. Jayabrata Ghosh-Dastidar, Nur A. Touba
    A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:79-88 [Conf]
  6. Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba
    Scan Vector Compression/Decompression Using Statistical Coding. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:114-120 [Conf]
  7. Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar
    On Diagnosing Path Delay Faults in an At-Speed Environment. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:28-33 [Conf]
  8. Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
    An efficient test vector compression scheme using selective Huffman coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:797-806 [Journal]

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