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Debjyoti Ghosh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:191-198 [Conf]
  2. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  3. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    A Technique to Reduce Power and Test Application Time in BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:182-183 [Conf]
  4. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
    Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:453-458 [Conf]
  5. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
    Low-power scan design using first-level supply gating. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:384-395 [Journal]

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