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Fernando M. Gonçalves: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos
    On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:263-270 [Conf]
  2. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:216-224 [Conf]
  3. Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:29-37 [Conf]
  4. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
    Fault Modeling and Defect Level Projections in Digital ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:436-442 [Conf]
  5. Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves
    A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:481-486 [Conf]
  6. José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura
    DARP - A Digital Audio Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:556-566 [Conf]
  7. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:164-165 [Conf]
  8. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:197-201 [Conf]
  9. M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:720-728 [Conf]
  10. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:377-385 [Conf]
  11. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Defect-oriented test quality assessment using fault sampling and simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:35-42 [Conf]
  12. M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
    Physical DFT for High Coverage of Realistic Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:642-651 [Conf]
  13. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
    IC Defects-Based Testability Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:500-509 [Conf]
  14. Fernando M. Gonçalves, João Paulo Teixeira
    Teaching Microelectronic-Based Integrated Systems Design and Test. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:65-66 [Conf]
  15. Fernando M. Gonçalves, João Paulo Teixeira
    Sampling Techniques of Non-Equally Probable Faults in VLSI System. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:283-288 [Conf]
  16. Marcelino B. Santos, F. M. Gongalves, Isabel C. Teixeira, João Paulo Teixeira
    Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:326-332 [Conf]
  17. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
    Defect level evaluation in an IC design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1286-1293 [Journal]

  18. A strategy for testability enhancement at layout level. [Citation Graph (, )][DBLP]


  19. On-Detector Electronics of the Clear PEM Scanner. [Citation Graph (, )][DBLP]


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