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Publications of Author

1. Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
   Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. [Citation Graph (0, 0)][DBLP]
   DFT, 1999, pp:121-129 [Conf]
   
2. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
   A novel reseeding technique for accumulator-based test pattern generation. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:7-12 [Conf]
   
3. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
   A New Reseeding Technique for LFSR-Based Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2001, pp:80-86 [Conf]
   
4. Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
   Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2002, pp:152-157 [Conf]
   
5. Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
   On the Design of Self-Testing Checkers for Modified Berger Codes. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2001, pp:153-157 [Conf]
   
6. Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
   Low Power BIST for Wallace Tree-Based Fast Multipliers. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:433-438 [Conf]
   
7. Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
   On Accumulator-Based Bit-Serial Test Response Compaction Schemes. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:350-0 [Conf]
   
8. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
   Low Power Testing by Test Vector Ordering with Vector Repetition. [Citation Graph (0, 0)][DBLP]
   ISQED, 2004, pp:205-210 [Conf]
   
9. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
   An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:261-266 [Conf]
   
10. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
    Scan Cell Ordering for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:281-284 [Conf]
    
11. Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
    An Efficient Test Vector Ordering Method for Low Power Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:285-288 [Conf]
    
12. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
    Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:804-811 [Conf]
    
13. Dimitris Bakalis, K. Adaos, George Alexiou, Dimitris Nikolos, D. Lymperopoulos
    EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2001, pp:182-187 [Conf]
    
14. Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
    A core generator for arithmetic cores and testing structures with a network interface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:1, pp:1-12 [Journal]
    
15. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
    On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:125-135 [Journal]
    
16. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
    A new built-in TPG method for circuits with random patternresistant faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:859-866 [Journal]
    
17. 
    On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. [Citation Graph (, )][DBLP]
    
    
18. 
    Combined SD-RNS Constant Multiplication. [Citation Graph (, )][DBLP]