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Jim Plusquellic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic
    Securing Scan Design Using Lock and Key Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:51-62 [Conf]
  2. Sanat Kamal Bahl, Jim Plusquellic
    FPGA implementation of a fast Hadamard transformer for WCDMA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:237- [Conf]
  3. Abhishek Singh, Jitin Tharian, Jim Plusquellic
    Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:748-753 [Conf]
  4. Dhruva Acharyya, Jim Plusquellic
    Impedance Profile of a Commercial Power Grid and Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:709-718 [Conf]
  5. Chintan Patel, Abhishek Singh, Jim Plusquellic
    Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:319-328 [Conf]
  6. Abhishek Singh, Chintan Patel, Jim Plusquellic
    On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:262-270 [Conf]
  7. Dhruva Acharyya, Jim Plusquellic
    Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:433-438 [Conf]
  8. Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
    At-Speed Transition Fault Testing With Low Speed Scan Enable. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:42-47 [Conf]
  9. Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic
    A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:94-99 [Conf]
  10. Chintan Patel, Jim Plusquellic
    A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:145-152 [Conf]
  11. Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
    Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:357-366 [Conf]
  12. Abhishek Singh, Chintan Patel, Jim Plusquellic
    Fault Simulation Model for i{DDT} Testing: An Investigation. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:304-312 [Conf]
  13. Dhananjay S. Phatak, Tom Goff, Jim Plusquellic
    IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2003, v:43, n:6, pp:787-804 [Journal]
  14. Jim Plusquellic
    IC Diagnosis Using Multiple Supply Pad IDDQs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:50-61 [Journal]
  15. Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel
    Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:278-293 [Journal]
  16. Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic
    Securing Designs against Scan-Based Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2007, v:4, n:4, pp:325-336 [Journal]
  17. Chintan Patel, Abhishek Singh, Jim Plusquellic
    Defect Detection Using Quiescent Signal Analysis. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:463-483 [Journal]
  18. Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel
    Defect Simulation Methodology for iDDT Testing. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:255-272 [Journal]

  19. A physical unclonable function defined using power distribution system equivalent resistance variations. [Citation Graph (, )][DBLP]


  20. Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. [Citation Graph (, )][DBLP]


  21. Power supply signal calibration techniques for improving detection resolution to hardware Trojans. [Citation Graph (, )][DBLP]


  22. Characterizing within-die variation from multiple supply port IDDQ measurements. [Citation Graph (, )][DBLP]


  23. Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals. [Citation Graph (, )][DBLP]


  24. Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. [Citation Graph (, )][DBLP]


  25. New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. [Citation Graph (, )][DBLP]


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