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Carlos Arthur Lang Lisbôa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carlos Arthur Lang Lisbôa, Luigi Carro
    Arithmetic Operators Robust to Multiple Simultaneous Upsets. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:289-297 [Conf]
  2. Á. Michels, L. Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro
    SET Fault Tolerant Combinational Circuits Based on Majority Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:345-352 [Conf]
  3. Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
    Online hardening of programs against SEUs and SETs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:280-290 [Conf]
  4. Carlos Arthur Lang Lisbôa, Luigi Carro
    An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:180- [Conf]
  5. Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro
    Going beyond TMR for protection against multiple faults. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:80-85 [Conf]
  6. E. L. Rhod, C. A. Lisboa, Luigi Carro
    A low-SER efficient core processor architecture for future technologies. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1448-1453 [Conf]
  7. C. A. Lisboa, Marcelo Ienczczak Erigson, Luigi Carro
    System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:165-172 [Conf]

  8. XOR-based Low Cost Checkers for Combinational Logic. [Citation Graph (, )][DBLP]

  9. A fast error correction technique for matrix multiplication algorithms. [Citation Graph (, )][DBLP]

  10. Invariant checkers: An efficient low cost technique for run-time transient errors detection. [Citation Graph (, )][DBLP]

  11. Increasing memory yield in future technologies through innovative design. [Citation Graph (, )][DBLP]

  12. A soft error robust and power aware memory design. [Citation Graph (, )][DBLP]

  13. Using majority logic to cope with long duration transient faults. [Citation Graph (, )][DBLP]

  14. Reliability aware yield improvement technique for nanotechnology based circuits. [Citation Graph (, )][DBLP]

  15. Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. [Citation Graph (, )][DBLP]

  16. New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies. [Citation Graph (, )][DBLP]

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