Search the dblp DataBase

Publications of Author

1. Jimson Mathew, Elena Dubrova
   Self-Checking 1-out-of-n CMOS Current-Mode Checker. [Citation Graph (0, 0)][DBLP]
   DFT, 2002, pp:69-77 [Conf]
   
2. Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
   An efficient technique for synthesis and optimization of polynomials in GF(2^m). [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:151-157 [Conf]
   
3. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
   SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:380-385 [Conf]
   
4. Jimson Mathew, D. Radhakrishnan, T. Srikanthan
   Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}. [Citation Graph (0, 0)][DBLP]
   NSIP, 1999, pp:185-188 [Conf]
   
5. H. Rahaman, Jimson Mathew, Dhiraj K. Pradhan
   Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:479-484 [Conf]
   
6. H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan
   Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP]
   VTS, 2007, pp:422-430 [Conf]
   
7. Jimson Mathew, H. Rahaman, Dhiraj K. Pradhan
   Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2007, pp:207-208 [Conf]
   
8. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
   CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3675-3678 [Conf]
   
9. R. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan
   On the Hardware Reduction of z-Datapath of Vectoring CORDIC. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3002-3005 [Conf]
   
10. Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew
    Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:141-144 [Conf]
    
11. 
    A Triple-Mode Sigma-Delta Modulator Design for Wireless Standards. [Citation Graph (, )][DBLP]
    
    
12. 
    Single Event Upset Detection and Correction. [Citation Graph (, )][DBLP]
    
    
13. 
    De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. [Citation Graph (, )][DBLP]
    
    
14. 
    Single ended 6T SRAM with isolated read-port for low-power embedded systems. [Citation Graph (, )][DBLP]
    
    
15. 
    Fault Tolerant Reversible Finite Field Arithmetic Circuits. [Citation Graph (, )][DBLP]
    
    
16. 
    Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. [Citation Graph (, )][DBLP]
    
    
17. 
    C-testable S-box implementation for secure advanced encryption standard. [Citation Graph (, )][DBLP]
    
    
18. 
    A nano-CMOS process variation induced read failure tolerant SRAM cell. [Citation Graph (, )][DBLP]
    
    
19. 
    Fault tolerant bit parallel finite field multipliers using LDPC codes. [Citation Graph (, )][DBLP]
    
    
20. 
    On the design of different concurrent EDC schemes for S-Box and GF(p). [Citation Graph (, )][DBLP]
    
    
21. 
    Layout-aware Illinois Scan design for high fault coverage coverage. [Citation Graph (, )][DBLP]
    
    
22. 
    Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. [Citation Graph (, )][DBLP]
    
    
23. 
    Design of Reversible Finite Field Arithmetic Circuits with Error Detection. [Citation Graph (, )][DBLP]
    
    
24. 
    A Galois Field Based Logic Synthesis Approach with Testability. [Citation Graph (, )][DBLP]
    
    
25. 
    Single Error Correcting Finite Field Multipliers Over GF(2m). [Citation Graph (, )][DBLP]
    
    
26. 
    Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. [Citation Graph (, )][DBLP]
    
    
27. 
    On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. [Citation Graph (, )][DBLP]
    
    
28. 
    A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. [Citation Graph (, )][DBLP]
    
    
29. 
    Failure analysis for ultra low power nano-CMOS SRAM under process variations. [Citation Graph (, )][DBLP]
    
    
30. 
    Pseudo parallel architecture for AES with error correction. [Citation Graph (, )][DBLP]
    
    
31. 
    GA-based Optimization of Sigma-delta Modulators for Wireless Transceivers. [Citation Graph (, )][DBLP]