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Ilya Levin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. A. Matrosova, Sergey Ostanin, Ilya Levin
    Survivable Self-Checking Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:395-402 [Conf]
  2. Vladimir Ostrovsky, Ilya Levin
    Implementation of Concurrent Checking Circuits by Independent Sub-circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:343-351 [Conf]
  3. Roman Goot, Ilya Levin, Sergei Ostanin
    Fault Latencies of Concurrent Checking FSMs. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:174-179 [Conf]
  4. Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky
    Synthesis of ASM-based Self-Checking Controllers. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:87-93 [Conf]
  5. Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov
    Cascade Scheme for Concurrent Errors Detection. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:359-368 [Conf]
  6. Ilya Levin, Vladimir Ostrovsky, Sergey Ostanin, Mark G. Karpovsky
    Self-checking sequential circuits with self-healing ability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:71-76 [Conf]
  7. Ilya Levin, Vladimir Sinelnikov
    Self-Checking of FPGA-Based Control Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:292-295 [Conf]
  8. Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin
    Sequential Circuits Applicable for Detecting Different Types of Faults. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:44-0 [Conf]
  9. A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin
    Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:49-53 [Conf]
  10. Victor Varshavsky, Ilya Levin, Vladimir Ostrovsky
    Increasing Implementability of beta-driven Threshold Checkers. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:158- [Conf]

  11. Reduction of Fault Latency in Sequential Circuits by using Decomposition. [Citation Graph (, )][DBLP]


  12. Arbitrary Error Detection in Combinational Circuits by Using Partitioning. [Citation Graph (, )][DBLP]


  13. Designing fault tolerant FSM by nano-PLA. [Citation Graph (, )][DBLP]


  14. Design of Design Methodology for Autonomous Robots. [Citation Graph (, )][DBLP]


  15. Use of gray decoding for implementation of symmetric functions. [Citation Graph (, )][DBLP]


  16. Personalizing Education in Post-Industrial Society. [Citation Graph (, )][DBLP]


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