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Kazuteru Namba: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kazuteru Namba, Eiji Fujiwara
    Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:299-307 [Conf]
  2. Yoichi Sasaki, Kazuteru Namba, Hideo Ito
    Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:327-335 [Conf]
  3. Kazuteru Namba, Hideo Ito
    Design of Defect Tolerant Wallace Multiplier. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:300-304 [Conf]
  4. Kazuteru Namba, Eiji Fujiwara
    A class of systematic m-ary single-symbol error correcting codes. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:6, pp:21-28 [Journal]

  5. A Delay Measurement Technique Using Signature Registers. [Citation Graph (, )][DBLP]

  6. Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. [Citation Graph (, )][DBLP]

  7. Testing of Switch Blocks in Three-Dimensional FPGA. [Citation Graph (, )][DBLP]

  8. Soft Error Hardened FF Capable of Detecting Wide Error Pulse. [Citation Graph (, )][DBLP]

  9. Delay Fault Testability on Two-Rail Logic Circuits. [Citation Graph (, )][DBLP]

  10. Dependability Evaluation for Internet-Based Remote Systems. [Citation Graph (, )][DBLP]

  11. Path Delay Fault Test Set for Two-Rail Logic Circuits. [Citation Graph (, )][DBLP]

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