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Publications of Author

1. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
   Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
   DFT, 2001, pp:314-0 [Conf]
   
2. Fabrice Monteiro, Abbas Dandache, Bernard Lepley
   Fast Configurable Polynomial Division for Error Control Coding Applications. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2001, pp:158-0 [Conf]
   
3. Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
   A High Speed Encoder for Recursive Systematic Convolutive Codes. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2002, pp:51-55 [Conf]
   
4. Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
   Designing a High Speed Decoder for Cyclic Codes. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2004, pp:129-134 [Conf]
   
5. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache
   Modeling of Transients Caused by a Laser Attack on Smart Cards. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2005, pp:193-194 [Conf]
   
6. T. Vallino, Abbas Dandache, J. P. Delahaye, Fabrice Monteiro, Bernard Lepley
   A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code. [Citation Graph (0, 0)][DBLP]
   IOLTW, 2000, pp:169-170 [Conf]
   
7. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel
   Characterizing Laser-Induced Pulses in ICs: Methodology and Results. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:11-16 [Conf]
   
8. A. Msir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
   Design of a high speed parallel encoder for convolutional codes. [Citation Graph (0, 0)][DBLP]
   Microelectronics Journal, 2004, v:35, n:2, pp:151-166 [Journal]
   
9. Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
   Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2007, pp:199-200 [Conf]
   
10. Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
    Designing fault-secure parallel encoders for systematic linear error correcting codes. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Reliability, 2003, v:52, n:4, pp:492-500 [Journal]
    
11. 
    A fault tolerant journalized stack processor architecture. [Citation Graph (, )][DBLP]
    
    
12. 
    An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders. [Citation Graph (, )][DBLP]