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Wieslaw Kuzmicz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
    CMOS Standard Cells Characterization for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:390-398 [Conf]
  2. Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz
    CMOS Standard Cells Characterization for Defect Based Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:384-0 [Conf]
  3. André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
    Integrated Design and Test Generation Under Internet Based Environment MOSCITO. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:187-195 [Conf]
  4. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
    Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:79-82 [Conf]
  5. Wieslaw Kuzmicz
    Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:315-320 [Conf]
  6. Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:365-371 [Conf]
  7. Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz
    Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:172-176 [Conf]
  8. Adam Wojtasik, Zbigniew Jaworski, Wieslaw Kuzmicz, Andrzej Wielgus, Andrzej Wakanis, Dariusz Sarna
    Fuzzy logic controller for rate-adaptive heart pacemaker. [Citation Graph (0, 0)][DBLP]
    Appl. Soft Comput., 2004, v:4, n:3, pp:259-270 [Journal]
  9. Wieslaw Kuzmicz
    Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:204-214 [Journal]
  10. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:12, pp:2023-2040 [Journal]
  11. T. Cibáková, M. Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Hierarchical test generation for combinational circuits with real defects coverage. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:7, pp:1141-1149 [Journal]

  12. Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. [Citation Graph (, )][DBLP]

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