The SCEAS System
Navigation Menu

Search the dblp DataBase


Bruce F. Cockburn: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott
    An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:475-0 [Conf]
  2. C. Wickman, Duncan G. Elliott, Bruce F. Cockburn
    Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:319-0 [Conf]
  3. Bruce F. Cockburn
    The Emergence of High-Density Semiconductor-Compatible Spintronic Memory. [Citation Graph (0, 0)][DBLP]
    ICMENS, 2003, pp:321-326 [Conf]
  4. Bruce F. Cockburn, Y.-F. Nicole Sat
    Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:23-32 [Conf]
  5. Gershom Birk, Duncan G. Elliott, Bruce F. Cockburn
    A Comparative Simulation Study of Four Multilevel DRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:102-109 [Conf]
  6. Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott
    An Investigation into Crosstalk Noise in DRAM Structures. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:123-0 [Conf]
  7. Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung
    Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:117-122 [Conf]
  8. Bruce F. Cockburn
    Panel on Advanced Embedded Memory Technologies. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:177-178 [Conf]
  9. Bruce F. Cockburn
    Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:46-51 [Conf]
  10. Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott
    A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:14-19 [Conf]
  11. Daniel Salamon, Bruce F. Cockburn
    An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:86-0 [Conf]
  12. Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn
    Design of an Embedded Fully-Depleted SOI SRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:13-0 [Conf]
  13. Bruce F. Cockburn, Albert L.-C. Kwong
    Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:430-439 [Conf]
  14. John C. Koob, Sue Ann Ung, Ashwin S. Rao, Daniel A. Leder, Craig S. Joly, Kristopher C. Breen, Tyler L. Brandon, Michael Hume, Bruce F. Cockburn, Duncan G. Elliott
    Test and Characterization of a Variable-Capacity Multilevel DRAM. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:189-197 [Conf]
  15. Bruce F. Cockburn, Fabrizio Lombardi, Fred J. Meyer
    Guest Editors' Introduction: DRAM Architecture and Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:19-21 [Journal]
  16. Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott
    Fault Models and Tests for a 2-Bit-per-Cell MLDRAM. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:22-31 [Journal]
  17. John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, L. McIlrath
    Design of a 3-D fully depleted SOI computational RAM. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:358-369 [Journal]
  18. Bruce F. Cockburn, Keith Boyle
    Design and Characterization of a Digital Delay Locked Loop Synthesized from Black Box Standard Cells. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1214-1217 [Conf]

  19. A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing. [Citation Graph (, )][DBLP]

  20. FPGA-based accelerator for the verification of leading-edge wireless systems. [Citation Graph (, )][DBLP]

  21. A flexible layered architecture for accurate digital baseband algorithm development and verification. [Citation Graph (, )][DBLP]

  22. A Flexible Filter Processor for Fading Channel Simulation. [Citation Graph (, )][DBLP]

  23. A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels. [Citation Graph (, )][DBLP]

  24. On the efficiency and accuracy of hybrid pseudo-random number generators for FPGA-based simulations. [Citation Graph (, )][DBLP]

  25. A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. [Citation Graph (, )][DBLP]

  26. A single-FPGA multipath MIMO fading channel simulator. [Citation Graph (, )][DBLP]

  27. An Improved SOS-Based Fading Channel Emulator. [Citation Graph (, )][DBLP]

  28. An Accurate and Compact Rayleigh and Rician Fading Channel Simulator. [Citation Graph (, )][DBLP]

  29. A Single FPGA Filter-Based Multipath Fading Emulator. [Citation Graph (, )][DBLP]

  30. A Reconfigurable SOS-based Rayleigh Fading Channel Simulator. [Citation Graph (, )][DBLP]

  31. On the Effects of Colored Noise on the Performance of LDPC Codes. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.005secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002