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Jung Hwan Kim:
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Publications of Author
- Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao
Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays. [Citation Graph (0, 0)][DBLP] DFT, 1993, pp:255-262 [Conf]
- Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao
Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor Arrays. [Citation Graph (0, 0)][DBLP] DFT, 1994, pp:74-82 [Conf]
- Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. [Citation Graph (0, 0)][DBLP] DFT, 2000, pp:69-77 [Conf]
- Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. [Citation Graph (0, 0)][DBLP] Evolvable Hardware, 2000, pp:253-262 [Conf]
- Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. [Citation Graph (0, 0)][DBLP] FPGA, 2000, pp:116-125 [Conf]
- Jung Hwan Kim, Sung-Soon Choi, Byung Ro Moon
Neural Network Normalization for Genetic Search. [Citation Graph (0, 0)][DBLP] GECCO (2), 2004, pp:398-399 [Conf]
- Jung Hwan Kim, Sung-Soon Choi, Byung Ro Moon
Normalization for neural network in genetic search. [Citation Graph (0, 0)][DBLP] GECCO, 2005, pp:1581-1582 [Conf]
- Jung Hwan Kim, Byung Ro Moon
Genetic Elevator Group Control. [Citation Graph (0, 0)][DBLP] GECCO, 2000, pp:762- [Conf]
- Jung Hwan Kim, Byung Ro Moon
Neuron Reordering For Better Neuro-genetic Hybrids. [Citation Graph (0, 0)][DBLP] GECCO, 2002, pp:407-414 [Conf]
- Jung Hwan Kim, Byung Ro Moon
New Usage of SOM for Genetic Algorithms. [Citation Graph (0, 0)][DBLP] GECCO, 2003, pp:1101-1111 [Conf]
- Michael Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP] GECCO, 2000, pp:391- [Conf]
- Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. [Citation Graph (0, 0)][DBLP] ICES, 2000, pp:264-273 [Conf]
- Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim
Gene Finding Using Evolvable Reasoning Hardware. [Citation Graph (0, 0)][DBLP] ICES, 2003, pp:198-207 [Conf]
- Jung Hwan Kim, Phill K. Rhee
A Parallel Reconfiguration Algorithm for WSI/VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP] ICPP (1), 1991, pp:670-671 [Conf]
- Jung Hwan Kim
On-Line Detection of Errors in Homogeneous Multiprocessor Systems. [Citation Graph (0, 0)][DBLP] IEEE Real-Time Systems Symposium, 1986, pp:55-62 [Conf]
- Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. [Citation Graph (0, 0)][DBLP] Genetic Programming and Evolvable Machines, 2001, v:2, n:3, pp:211-230 [Journal]
- Harold Szu, Jung Hwan Kim, Insook Kim
Live neural network formations on electronic chips. [Citation Graph (0, 0)][DBLP] Neurocomputing, 1994, v:6, n:5, pp:551-564 [Journal]
- Jung Hwan Kim, Sudhakar M. Reddy
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1989, v:38, n:4, pp:515-0 [Journal]
- Jung Hwan Kim, Phill K. Rhee
The Rule-Based Approach to Reconfiguration of 2-D Processor Arrays. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1993, v:42, n:11, pp:1403-1408 [Journal]
- Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim
Finding transcriptional regulatory elements in Dictyostelium gene expression. [Citation Graph (0, 0)][DBLP] Congress on Evolutionary Computation, 2005, pp:1746-1752 [Conf]
- M. Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim
Fault-tolerant self-organizing map implemented by wafer-scale integration. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:257-265 [Journal]
The Segmental-Transmission-Line: Its Design and Prototype Evaluation. [Citation Graph (, )][DBLP]
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