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Robert D. McLeod: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zaifu Zhang, Robert D. McLeod, Witold Pedrycz
    Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:55-64 [Conf]
  2. Richard W. Wieler, Zaifu Zhang, Robert D. McLeod
    Emulating static faults using a Xilinx based emulator. [Citation Graph (0, 0)][DBLP]
    FCCM, 1995, pp:110-115 [Conf]
  3. David C. Blight, Robert D. McLeod
    Self-Organizing Kohonen Maps for FPL Placement. [Citation Graph (0, 0)][DBLP]
    FPL, 1992, pp:88-95 [Conf]
  4. C. Hart Poskar, Peter J. Czezowski, Robert D. McLeod
    A Computational Intelligence Based Coarse-Grained Reconfigurable Element. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:246- [Conf]
  5. Richard W. Wieler, Zaifu Zhang, Robert D. McLeod
    Simulating Static and Dynamic Faults in BIST Strucutres with a FPGA Based Emulator. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:240-250 [Conf]
  6. Zaifu Zhang, Robert D. McLeod
    An Efficient Multiple Scan Chain Testing Scheme. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:294-0 [Conf]
  7. Zaifu Zhang, Robert D. McLeod, G. E. Bridges
    Statistical estimation of delay fault detectabilities and fault grading. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:184-187 [Conf]
  8. Robert D. McLeod, Sheng Huang, Marek Laskowski, Sajid Hussain
    Communication Issues within HPC Grids. [Citation Graph (0, 0)][DBLP]
    HPCS, 2004, pp:101-107 [Conf]
  9. Robert D. McLeod, Dong Zhang, Sajid Hussain
    iSCSI Simulation for Internet Applications. [Citation Graph (0, 0)][DBLP]
    International Conference on Internet Computing, 2004, pp:285-289 [Conf]
  10. Babk S. Noghani, Steve Kretschmann, Robert D. McLeod
    Reducing Latency on the Internet using "Component-Based Download" and "File-Segment Transfer Protocol". [Citation Graph (0, 0)][DBLP]
    International Conference on Internet Computing, 2000, pp:465-472 [Conf]
  11. S. Huang, Robert D. McLeod
    Phatpackets for Data Transport within an HPC Network. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:154-160 [Conf]
  12. Sajid Huang, Robert D. McLeod
    Adaptive Network Load Balancing in Phatpackets. [Citation Graph (0, 0)][DBLP]
    Communications, Internet, and Information Technology, 2002, pp:154-159 [Conf]
  13. G. K. Rosendahl, Robert D. McLeod, Howard C. Card
    A DSP-FPGA-Based Reconfigurable Computer. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 1998, v:8, n:4, pp:453-459 [Journal]
  14. Howard C. Card, Adonios Thanailakis, Werner Pries, Robert D. McLeod
    Analysis of Bounded Linear Cellular Automata Based on a Method of Image Charges. [Citation Graph (0, 0)][DBLP]
    J. Comput. Syst. Sci., 1986, v:33, n:3, pp:473-480 [Journal]
  15. Robert D. McLeod, J. J. Schellenberg, Peter D. Hortensius
    Percolation and Anomalous Transport as Tools in Analyzing Parallel Processing Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:8, n:4, pp:376-387 [Journal]
  16. G. E. Bridges, Werner Pries, Robert D. McLeod, M. Yunik, P. Glenn Gulak, Howard C. Card
    Dual Systolic Architectures for VLSI Digital Signal Processing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:10, pp:916-923 [Journal]
  17. Howard C. Card, P. Glenn Gulak, Robert D. McLeod, Werner Pries
    (lambda, T) Complexity Measures for VLSI Computations in Constant Chip Area. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:1, pp:112-117 [Journal]
  18. Howard C. Card, G. K. Rosendahl, Dean K. McNeill, Robert D. McLeod
    Competitive Learning Algorithms and Neurocomputer Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:847-858 [Journal]
  19. Peter D. Hortensius, Robert D. McLeod, Howard C. Card
    Parallel Random Number Generation for VLSI Systems Using Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:10, pp:1466-1473 [Journal]
  20. Peter D. Hortensius, Howard C. Card, Robert D. McLeod, Werner Pries
    Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:6, pp:769-774 [Journal]
  21. Peter D. Hortensius, Robert D. McLeod, Howard C. Card
    Cellular Automata-Based Signature analysis for Built-in Self-Test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:10, pp:1273-1283 [Journal]
  22. Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. M. Miller, Howard C. Card
    Cellular automata-based pseudorandom number generators for built-in self-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:8, pp:842-859 [Journal]
  23. David C. Blight, Robert D. McLeod
    An adaptive message passing environment for water scale systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:559-562 [Journal]
  24. C. Sul, Robert D. McLeod, Witold Pedrycz
    Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:2, pp:224-228 [Journal]
  25. R. V. Pelletier, Robert D. McLeod
    Loop based design for wafer scale systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:354-357 [Journal]

  26. Vehicular telematics over heterogeneous wireless networks: A survey. [Citation Graph (, )][DBLP]


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