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Publications of Author

1. Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, A.-M. Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
   Hardware Virtual Components Compliant with Communication System Standards. [Citation Graph (0, 0)][DBLP]
   DSD, 2005, pp:88-95 [Conf]
   
2. Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
   A Computation Core for Communication Refinement of Digital Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:240-250 [Conf]
   
3. Christophe Jégo, Emmanuel Casseau, Eric Martin
   Architectural Synthesis with Interconnection Cost Control. [Citation Graph (0, 0)][DBLP]
   VLSI, 1999, pp:509-520 [Conf]
   
4. Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
   Reed-Solomon behavioral virtual component for communication systems. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2004, pp:173-176 [Conf]
   
5. Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin
   Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2005, pp:268-269 [Conf]
   
6. Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
   Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2005, pp:240-243 [Conf]
   
7. Emmanuel Casseau, Dominique Degrugillier
   A Linear Systolic Array for LU Decomposition. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:353-358 [Conf]
   
8. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
   Constrained algorithmic IP design for system-on-chip. [Citation Graph (0, 0)][DBLP]
   Integration, 2007, v:40, n:2, pp:94-105 [Journal]
   
9. Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin
   A formal method for hardware IP design and integration under I/O and timing constraints. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Embedded Comput. Syst., 2006, v:5, n:1, pp:29-53 [Journal]
   
10. Emmanuel Casseau, Christophe Jégo, Eric Martin
    Synthèse architecturale d'applications temps réel pour technologies submicroniques. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2004, v:23, n:1, pp:35-66 [Journal]
    
11. Guillaume Savaton, Emmanuel Casseau, Eric Martin
    Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:7, pp:1375-1399 [Journal]
    
12. Fatma Sayadi, Emmanuel Casseau, Mohamed Atri, Mehrez Marzougui, Rached Tourki, Eric Martin
    G729 Voice Decoder Design. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:173-184 [Journal]
    
13. 
    Reconfigurable SWP Operator for Multimedia Processing. [Citation Graph (, )][DBLP]
    
    
14. 
    A design flow dedicated to multi-mode architectures for DSP applications. [Citation Graph (, )][DBLP]
    
    
15. 
    High-level synthesis for the design of FPGA-based signal processing systems. [Citation Graph (, )][DBLP]
    
    
16. 
    Synthesis of Multimode digital signal processing systems. [Citation Graph (, )][DBLP]
    
    
17. 
    Reconfigurable Operator Based Multimedia Embedded Processor. [Citation Graph (, )][DBLP]
    
    
18. 
    Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications. [Citation Graph (, )][DBLP]
    
    
19. 
    Hardware Communication Refinement in Digital Signal Processing. [Citation Graph (, )][DBLP]
    
    
20. 
    Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. [Citation Graph (, )][DBLP]