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Christophe Jégo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nabil Abdelli, Pierre Bomel, Emmanuel Casseau, A.-M. Fouilliart, Christophe Jégo, Philippe Kajfasz, Bertrand Le Gal, Nathalie Le Heno
    Hardware Virtual Components Compliant with Communication System Standards. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:88-95 [Conf]
  2. Caaliph Andriamisaina, Catherine Dezan, Christophe Jégo, Bernard Pottier
    Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit. [Citation Graph (0, 0)][DBLP]
    ERSA, 2005, pp:263-266 [Conf]
  3. Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec
    The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  4. Christophe Jégo, Emmanuel Casseau, Eric Martin
    Architectural Synthesis with Interconnection Cost Control. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:509-520 [Conf]
  5. Emmanuel Casseau, Bertrand Le Gal, Christophe Jégo, Nathalie Le Heno, Eric Martin
    Reed-Solomon behavioral virtual component for communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:173-176 [Conf]
  6. Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
    A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:430-431 [Conf]
  7. Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
    Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:152-159 [Conf]
  8. Emmanuel Casseau, Christophe Jégo, Eric Martin
    Synthèse architecturale d'applications temps réel pour technologies submicroniques. [Citation Graph (0, 0)][DBLP]
    Technique et Science Informatiques, 2004, v:23, n:1, pp:35-66 [Journal]
  9. Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
    Towards Gb/s turbo decoding of product code onto an FPGA device. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:909-912 [Conf]
  10. Erwan Piriou, Christophe Jégo, Patrick Adde, R. Le Bidan, Michel Jézéquel
    Efficient architecture for Reed Solomon block turbo code. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  11. Irene M. Mahafeno, Charlotte Langlais, Christophe Jégo
    Reduced Complexity Iterative Multi-User Detector for IDMA (Interleave-Division Multiple Access) System. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]

  12. FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems. [Citation Graph (, )][DBLP]


  13. Blind Frame Synchronization of Product Codes Based on the Adaptation of the Parity Check Matrix. [Citation Graph (, )][DBLP]


  14. Energy Efficient Turbo Decoder with Reduced State Metric Quantization. [Citation Graph (, )][DBLP]


  15. A highly parallel Turbo Product Code decoder without interleaving resource. [Citation Graph (, )][DBLP]


  16. Design of rotated QAM mapper/demapper for the DVB-T2 standard. [Citation Graph (, )][DBLP]


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