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Daniel Eckerbert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel Eckerbert, Per Larsson-Edefors
    Interconnect-Driven Short-Circuit Power Modeling. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:414-421 [Conf]
  2. Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
    A Mixed-Mode Delay-Locked-Loop Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:261-263 [Conf]
  3. Daniel Eckerbert, Per Larsson-Edefors
    Cycle-true leakage current modeling for CMOS gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:507-510 [Conf]
  4. Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson
    Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:225-230 [Conf]
  5. Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
    Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:370-379 [Journal]

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