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Steffen Rülke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig
    Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:364-370 [Conf]
  2. Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke
    Cost-Efficient Implementation of Adaptive Finite State Machines. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:144-151 [Conf]
  3. Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke
    Enhanced Reusability for SoC-Based HW/SW Co-Design. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:94-101 [Conf]
  4. Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
    Two-Criterial Constraint-Driven FSM State Encoding for Low Power. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:94-101 [Conf]
  5. Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
    Low Power Design of FSMs by State Assignment and Disabling Self-Loops. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1997, pp:323-330 [Conf]
  6. Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
    Multi-Criterial State Assignment for Low Power FSM Design. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10261-10268 [Conf]
  7. Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger
    A Low-Cost Realization of an Adaptable Protocol Processing Unit. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  8. Maik Boden, Steffen Rülke, Jürgen Becker
    A high-level target-precise model for designing reconfigurable HW tasks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  9. Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
    IPQ: IP Qualification for Efficient System Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:478-482 [Conf]
  10. Jörg Schneider, Vincent Kotzsch, Steffen Rülke
    Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:177-180 [Conf]
  11. Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker
    High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  12. Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
    A Tailored Design Partitioning Method for Hardware Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:99-105 [Conf]

  13. Automatic Generation of Complex Properties for Hardware Designs. [Citation Graph (, )][DBLP]


  14. A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. [Citation Graph (, )][DBLP]


  15. GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. [Citation Graph (, )][DBLP]


  16. An Integrated SystemC Debugging Environment. [Citation Graph (, )][DBLP]


  17. Non-Intrusive High-level SystemC Debugging. [Citation Graph (, )][DBLP]


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