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Oswaldo Cadenas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oswaldo Cadenas, Graham M. Megson
    Pipelining Considerations for an FPGA Case. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:276-285 [Conf]
  2. Oswaldo Cadenas, Graham M. Megson
    Improving mW/MHz Ratio in FPGAs Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:276-282 [Conf]
  3. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    Implementation of a block based neural branch predictor. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:235-238 [Conf]
  4. Oswaldo Cadenas, Graham M. Megson, Toomas P. Plaks
    FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:201-207 [Conf]
  5. Oswaldo Cadenas, Graham M. Megson
    A n-Bit Reconfigurable Scalar Quantiser. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:420-429 [Conf]
  6. Oswaldo Cadenas, Graham M. Megson
    A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:322-331 [Conf]
  7. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    FPGA Organization for the Fast Path-Based Neural Branch Predictor. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:251-258 [Conf]
  8. Oswaldo Cadenas, Graham M. Megson, Daniel Jones
    A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:305-306 [Conf]
  9. Oswaldo Cadenas, Graham M. Megson
    Pullpipelining: A technique for systolic pipelined circuits. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:205-210 [Conf]
  10. Toomas P. Plaks, Oswaldo Cadenas, Graham M. Megson
    Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:1131-1137 [Conf]
  11. Oswaldo Cadenas, Graham M. Megson
    A FPGA pipelined backward adaptive scalar quantizer. [Citation Graph (0, 0)][DBLP]
    Circuits, Signals, and Systems, 2004, pp:410-415 [Conf]
  12. Oswaldo Cadenas, Graham M. Megson
    A clocking technique for FPGA pipelined designs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:11, pp:687-696 [Journal]
  13. Oswaldo Cadenas, Graham M. Megson
    Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]

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