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Gaetano Palumbo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giuseppe Notarangelo, Marco Gibilaro, Francesco Pappalardo 0002, Agatino Pennisi, Gaetano Palumbo
    Low Power Strategy for a TFT Controller. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:351-354 [Conf]
  2. Massimo Alioto, Gaetano Palumbo
    Novel Simple Models Of Cml Propagation Delay. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:270-274 [Conf]
  3. Gianluca Giustolisi, Giovanni Palmisano, Gaetano Palumbo, C. Strano
    A Novel 1.5-V Cmos Mixer. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:113-117 [Conf]
  4. Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton
    Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2001, pp:192-196 [Conf]
  5. Massimo Alioto, Gaetano Palumbo
    Design of MUX, XOR and D-latch SCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:261-264 [Conf]
  6. Massimo Alioto, Gaetano Palumbo
    Design techniques for low-power cascaded CML gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4685-4688 [Conf]
  7. Walter Aloisi, Stello Matteo Billé, Gaetano Palumbo
    Low-voltage linear voltage regulator suitable for memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:389-392 [Conf]
  8. Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
    A 1-V CMOS output stage with high linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:225-228 [Conf]
  9. Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
    Design of low-voltage low-power SC filters for high-frequency applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:605-608 [Conf]
  10. Giuseppe Di Cataldo, Gaetano Palumbo
    Optimized Design of 4 Stage Dickson Voltage Multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:693-696 [Conf]
  11. Giuseppe Di Cataldo, Giovanni Palmisano, Gaetano Palumbo
    A CMOS CCII+. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:315-318 [Conf]
  12. Gianluca Giustolisi, Gaetano Palumbo
    A novel 1-V class-AB transconductor for improving speed performance in SC applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:153-156 [Conf]
  13. Gianluca Giustolisi, Gaetano Palumbo
    A new method for evaluating harmonic distortion in push-pull output stages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:233-236 [Conf]
  14. Gianluca Giustolisi, Gaetano Palumbo
    Sigma-Delta A/D fuzzy converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:677-680 [Conf]
  15. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:525-528 [Conf]
  16. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Well-defined design procedure for a three-stage CMOS OTA. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2579-2582 [Conf]
  17. Giovanni Palmisano, Gaetano Palumbo, Salvatore Pennisi
    A High-Accuracy High-Speed CMOS Current Comparator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:739-742 [Conf]
  18. Gaetano Palumbo
    Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:413-416 [Conf]
  19. Gaetano Palumbo, Salvatore Pennisi
    Harmonic distortion in three-stage nested-Miller-compensated amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:485-488 [Conf]
  20. Gianluca Giustolisi, Gaetano Palumbo
    Detailed frequency analysis of power supply rejection in Brokaw bandgap. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:731-734 [Conf]
  21. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Reversed nested Miller compensation with current follower. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:308-311 [Conf]
  22. Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
    CML ring oscillators: oscillation frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:112-115 [Conf]
  23. Gaetano Palumbo, D. Pappalardo, M. Gaibotti
    Modeling and minimization of power consumption in charge pump circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:402-405 [Conf]
  24. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    A gate-level strategy to design Carry Select Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:465-468 [Conf]
  25. Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo
    Analysis and optimization of gain-boosted telescopic amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:321-324 [Conf]
  26. Gianluca Giustolisi, Gaetano Palumbo
    Analysis of power supply noise attenuation in a PTAT current source. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:561-564 [Conf]
  27. Massimo Alioto, Gaetano Palumbo
    Power-delay trade-offs in SCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:249-252 [Conf]
  28. Gaetano Palumbo, F. Pappalardo, S. Sannella
    Evaluation on power reduction applying gated clock approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:85-88 [Conf]
  29. Massimo Alioto, Gaetano Palumbo
    Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:265-275 [Conf]
  30. Massimo Alioto, Gaetano Palumbo
    Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:429-437 [Conf]
  31. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    An Approach to Energy Consumption Modeling in RC Ladder Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:239-246 [Conf]
  32. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:355-363 [Conf]
  33. Rosario Mita, Gaetano Palumbo
    Modeling of Propagation Delay of a First Order Circuit with a Ramp Input. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:468-476 [Conf]
  34. Massimo Alioto, Rosario Mita, Gaetano Palumbo
    Performance evaluation of the low-voltage CML D-latch topology. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:36, n:4, pp:191-209 [Journal]
  35. Massimo Alioto, Gaetano Palumbo
    Highly accurate and simple models for CML and ECL gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1369-1375 [Journal]
  36. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Evaluation of energy consumption in RC ladder circuits driven by a ramp input. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1094-1107 [Journal]
  37. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:452-461 [Journal]
  38. Rosario Mita, Gaetano Palumbo, Pier Giorgio Fallica
    A fast driver circuit for single-photon sensors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:10, pp:1092-1096 [Journal]
  39. Massimo Alioto, Gaetano Palumbo
    High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2998-3001 [Conf]
  40. Massimo Alioto, Gaetano Palumbo
    Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3255-3258 [Conf]
  41. Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo
    Rosenstark-like Representation of Feedback Amplifier Resistance. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2212-2215 [Conf]
  42. Walter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi
    Miller Compensation: Optimization with Current Buffer/Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2216-2219 [Conf]
  43. Massimo Alioto, Gaetano Palumbo
    Delay uncertainty due to supply variations in static and dynamic full adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  44. Massimo Alioto, Gaetano Palumbo
    Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3732-3735 [Conf]
  45. A. D. Grasso, Gaetano Palumbo, Salvatore Pennisi
    Active reversed nested Miller compensation for three-stage amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  46. Massimo Alioto, Gaetano Palumbo
    Nanometer MCML gates: models and design considerations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  47. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  48. Gaetano Palumbo, M. Pennisi, Salvatore Pennisi
    Analysis and evaluation of harmonic distortion in the tunnel diode oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  49. Massimo Alioto, Gaetano Palumbo
    Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1322-1335 [Journal]
  50. Massimo Alioto, Gaetano Palumbo
    Power estimation in adiabatic circuits: a simple and accurate model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:608-615 [Journal]
  51. Massimo Alioto, Gaetano Palumbo
    Analysis and comparison on full adder block in submicron technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:806-823 [Journal]

  52. Power-delay optimization in MCML tapered buffers. [Citation Graph (, )][DBLP]


  53. Explicit energy evaluation in RLC tree circuits with ramp inputs. [Citation Graph (, )][DBLP]


  54. Low-voltage LDO Compensation Strategy based on Current Amplifiers. [Citation Graph (, )][DBLP]


  55. Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. [Citation Graph (, )][DBLP]


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