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Publications of Author

1. Ilia Oussorov, Wolfgang Raab, J. A. Ulrich Hachmann, Alex Kravtsov
   Integration of Instruction Set Simulators into SystemC High Level Models. [Citation Graph (0, 0)][DBLP]
   DSD, 2002, pp:126-131 [Conf]
   
2. Hans-Martin Blüthgen, Christian Sauer, Dominik Langen, Matthias Gries, Wolfgang Raab
   Application-Driven Design of Cost-Efficient Communications Platforms. [Citation Graph (0, 0)][DBLP]
   GI Jahrestagung (1), 2005, pp:314-318 [Conf]
   
3. Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer
   SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. [Citation Graph (0, 0)][DBLP]
   IPPS, 1995, pp:774-781 [Conf]
   
4. Ulrich Ramacher, Wolfgang Raab, Wolfgang Kabatzke
   Prototyp eines Bildrechners für Echtzeitbildverarbeitung in Industrie- und Medientechnik. [Citation Graph (0, 0)][DBLP]
   PEARL, 1999, pp:102-110 [Conf]
   
5. Wolfgang Raab, Hans-Martin Blüthgen, Ulrich Ramacher
   A low-power memory hierarchy for a fully programmable baseband processor. [Citation Graph (0, 0)][DBLP]
   WMPI, 2004, pp:102-106 [Conf]
   
6. Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer
   A 100-GOPS Programmable Processor for Vehicle Vision Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:1, pp:8-16 [Journal]
   
7. Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz
   Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 1993, v:4, n:4, pp:333-336 [Journal]
   
8. Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer
   100 GOPS vision processor for automotive applications. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:60-68 [Journal]
   
9. 
   A 150Mbit/s 3GPP LTE Turbo code decoder. [Citation Graph (, )][DBLP]
   
   
10. 
    Low power design of the X-GOLD^® SDR 20 baseband processor. [Citation Graph (, )][DBLP]