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Henry Selvaraj: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
    NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:248-254 [Conf]
  2. Jianhong Li, Laxmi Gewali, Henry Selvaraj, Muthukumar Venkatesan
    Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:574-578 [Conf]
  3. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
    An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:104-111 [Conf]
  4. Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki
    Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:136-143 [Conf]
  5. Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
    Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:460-466 [Conf]
  6. Ling Wang, Henry Selvaraj
    A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:144-147 [Conf]
  7. Henry Selvaraj, B. Li
    A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1212-0 [Conf]
  8. Henry Selvaraj, Muthukumar Venkatesan
    A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10024-0 [Conf]
  9. Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
    An Improved Column Compatibility Approach for Partition Based Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1067-0 [Conf]
  10. Piotr Sapiecha, Henry Selvaraj, Jaroslaw Stanczak, Krzysztof Sep, Tadeusz Luba
    A Hybrid Approach to a Classification Problem. [Citation Graph (0, 0)][DBLP]
    Intelligent Information Systems, 2004, pp:99-106 [Conf]
  11. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Synthesis scheme for low power designs with multiple supply voltages by tabu search. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:261-264 [Conf]
  12. Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
    A variable partition approach for disjoint decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:157-162 [Conf]
  13. Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
    FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. [Citation Graph (0, 0)][DBLP]
    ITCC, 2002, pp:355-360 [Conf]
  14. Henry Selvaraj, Pawel Tomaszewicz, Mariusz Rawski, Tadeusz Luba
    Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2005, pp:22-27 [Conf]
  15. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:829-833 [Conf]
  16. Ling Wang, Henry Selvaraj
    Performance Driven Circuit Clustering and Partitioning. [Citation Graph (0, 0)][DBLP]
    ITCC, 2002, pp:352-354 [Conf]
  17. Min Tun, Laxmi Gewali, Henry Selvaraj
    Interference Aware Routing in Sensor Network. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:140-146 [Conf]
  18. Piotr Sapiecha, Henry Selvaraj, Michal Pleban
    Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis. [Citation Graph (0, 0)][DBLP]
    Rough Sets and Current Trends in Computing, 2000, pp:487-494 [Conf]
  19. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:272-278 [Conf]
  20. Muthukumar Venkatesan, Henry Selvaraj
    Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:51-57 [Conf]
  21. Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba
    Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:388-393 [Conf]
  22. Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
    Functional Decomposition and Its Applications in Machine Learning and Neural Networks. [Citation Graph (0, 0)][DBLP]
    International Journal of Computational Intelligence and Applications, 2001, v:1, n:3, pp:259-271 [Journal]
  23. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Scheduling and optimal voltage selection with multiple supply voltages under resource constraints. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:174-182 [Journal]
  24. Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj
    An efficient variable partitioning approach for functional decomposition of circuits. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:1, pp:53-67 [Journal]
  25. Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj
    Multiple voltage and frequency scheduling for power minimization. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:382-394 [Journal]
  26. Henry Selvaraj, Lech Józwiak
    Reconfigurable embedded systems: Synthesis, design and application. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:347-349 [Journal]
  27. Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
    An application of functional decomposition in ROM-based FSM implementation in FPGA devices. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:6-7, pp:424-434 [Journal]
  28. Ling Wang, Yingtao Jiang, Henry Selvaraj
    Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:35, n:1, pp:93-113 [Journal]

  29. Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors. [Citation Graph (, )][DBLP]


  30. Processor Allocation Problem for NoC-Based Chip Multiprocessors. [Citation Graph (, )][DBLP]


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