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Publications of Author

1. Toshinori Sato, Itsujiro Arita
   Simplifying Instruction Issue Logic in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
   DSD, 2002, pp:341-346 [Conf]
   
2. Toshinori Sato, Itsujiro Arita
   Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 2001, pp:428-438 [Conf]
   
3. Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita
   Influence of Compiler Optimizations on Value Prediction. [Citation Graph (0, 0)][DBLP]
   HPCN Europe, 2001, pp:312-321 [Conf]
   
4. Itsujiro Arita
   Intelligent console - A universal user interface of a computer system. [Citation Graph (0, 0)][DBLP]
   Operating Systems Engineering, 1980, pp:233-250 [Conf]
   
5. Takayuki Hirahara, Takashi Yamanoue, Hiroyuki Anzai, Itsujiro Arita
   Sending an Image to a Large Number of Nodes in Short Time using TCP. [Citation Graph (0, 0)][DBLP]
   IEEE International Conference on Multimedia and Expo (II), 2000, pp:987-990 [Conf]
   
6. Yasushi Shimono, Bernady O. Apduhan, Itsujiro Arita, Yoshimasa Ohnishi
   Evaluating the Performance of a DSM Cluster with Improved Communication Subsystem. [Citation Graph (0, 0)][DBLP]
   ICOIN, 2001, pp:561-567 [Conf]
   
7. Toshinori Sato, Itsujiro Arita
   Partial Resolution in Data Value Predictors. [Citation Graph (0, 0)][DBLP]
   ICPP, 2000, pp:69-76 [Conf]
   
8. Toshinori Sato, Itsujiro Arita
   In Search of Efficient Reliable Processor Design. [Citation Graph (0, 0)][DBLP]
   ICPP, 2001, pp:525-532 [Conf]
   
9. Tatsuya Asazu, Bernady O. Apduhan, Itsujiro Arita
   Towards a Portable Cluster Computing Environment Supporting Single System Image. [Citation Graph (0, 0)][DBLP]
   ICPP Workshops, 1999, pp:488-0 [Conf]
   
10. Toshinori Sato, Itsujiro Arita
    Table size reduction for data value predictors by exploiting narrow width values. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:196-205 [Conf]
    
11. Toshinori Sato, Itsujiro Arita
    Low-Cost Value Predictors Using Frequent Value Locality. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:106-119 [Conf]
    
12. Toshinori Sato, Itsujiro Arita
    Comprehensive Evaluation of an Instruction Reissue Mechanism. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2000, pp:78-87 [Conf]
    
13. Toshinori Sato, Itsujiro Arita
    Reducing Energy Consumption via Low-Cost Value Prediction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:380-389 [Conf]
    
14. Toshinori Sato, Itsujiro Arita
    The KIT COSMOS Processor: Introducing CONDOR. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
    
15. Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita
    The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1010-1016 [Conf]
    
16. Toshinori Sato, Itsujiro Arita
    Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:225-232 [Conf]
    
17. Toshinori Sato, Itsujiro Arita
    Combining variable latency pipeline with instruction reuse for execution latency reduction. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2003, v:34, n:12, pp:11-21 [Journal]
    
18. Koichiro Tanaka, Itsujiro Arita
    The development and evaluation of SHOKE2000: The PCI-based FPGA card. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:9, pp:50-57 [Journal]
    
19. Takenori Koushiro, Toshinori Sato, Itsujiro Arita
    A trace-level value predictor for Contrail processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:3, pp:42-47 [Journal]
    
20. Toshinori Sato, Itsujiro Arita
    Tolerating Transient Faults through an Instruction Reissue Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:240-247 [Conf]
    
21. 
    An Indoor Location-Aware Mobile Navigation Service for the Handicapped and the Elderly. [Citation Graph (, )][DBLP]