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João Canas Ferreira:
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Publications of Author
- Miguel L. Silva, João Canas Ferreira
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. [Citation Graph (0, 0)][DBLP] DSD, 2005, pp:383-387 [Conf]
- José Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos
FAFNER-Accelerating Nesting Problems with FPGAs. [Citation Graph (0, 0)][DBLP] FCCM, 1999, pp:168-0 [Conf]
- João Canas Ferreira, José Silva Matos
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] FCCM, 1998, pp:280-281 [Conf]
- João Canas Ferreira, José Silva Matos
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:886-890 [Conf]
- João Canas Ferreira, Miguel M. Silva
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. [Citation Graph (0, 0)][DBLP] IPDPS, 2005, pp:- [Conf]
- José Silva Matos, João Canas Ferreira, Ana C. Leão, José M. Silva
An Approach to Testability Improvement of Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP] ISCAS, 1994, pp:161-164 [Conf]
- José Silva Matos, Ana C. Leão, João Canas Ferreira
Control and Observation of Analog Nodes in Mixed-Signal Boards. [Citation Graph (0, 0)][DBLP] ITC, 1993, pp:323-331 [Conf]
- Miguel L. Silva, João Canas Ferreira
Support for partial run-time reconfiguration of platform FPGAs. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2006, v:52, n:12, pp:709-726 [Journal]
Generation of partial FPGA configurations at run-time. [Citation Graph (, )][DBLP]
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