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A. E. A. Almaini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yinshui Xia, A. E. A. Almaini
    Best Polarity for Low Power XOR Gate Decomposition. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:53-59 [Conf]
  2. Z. Guan, P. Thomson, A. E. A. Almaini
    A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:298-301 [Conf]
  3. Yinshui Xia, B. Ali, A. E. A. Almaini
    Area and power optimization of FPRM function based circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:329-332 [Conf]
  4. L. Wang, A. E. A. Almaini
    Multilevel Logic Minimization Using Functional Don't Cares. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:417-424 [Conf]
  5. M. MacCallum, A. E. A. Almaini
    The Application of the Wavelet Transform to Polysomnographic Signals. [Citation Graph (0, 0)][DBLP]
    WAA, 2001, pp:284-295 [Conf]
  6. B. Ali, A. E. A. Almaini, Tatiana Kalganova
    Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    Genetic Programming and Evolvable Machines, 2004, v:5, n:1, pp:11-29 [Journal]
  7. Yinshui Xia, Xunwei Wu, A. E. A. Almaini
    Power Minimization of FPRM Functions Based on Polarity Conversion. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:325-331 [Journal]
  8. Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini
    A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:237-242 [Journal]
  9. A. E. A. Almaini
    Sequential Machine Implementations Using Universal Logic Modules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:951-960 [Journal]

  10. Fast Conversion for Large Canonical OR-Coincidence Functions. [Citation Graph (, )][DBLP]


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