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Publications of Author

1. Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber
   A Mixed Language Fault Simulation of VHDL and SystemC. [Citation Graph (0, 0)][DBLP]
   DSD, 2006, pp:275-279 [Conf]
   
2. Silvio Misera, Heinrich Theodor Vierhaus
   FIT - A Parallel Hierarchical Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
   PARELEC, 2004, pp:289-294 [Conf]
   
3. 
   Fault Injection Techniques and their Accelerated Simulation in SystemC. [Citation Graph (, )][DBLP]
   
   
4. 
   Timing- / Power-Optimization for Digital Logic Based on Standard Cells. [Citation Graph (, )][DBLP]