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Sonia López: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:423-432 [Conf]
  2. José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López
    Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:495-505 [Conf]
  3. Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López
    A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:514-523 [Conf]
  4. Sonia López, Oscar Garnica, José Manuel Colmenar
    Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:623-632 [Conf]
  5. Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:151-160 [Conf]
  6. José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. [Citation Graph (0, 0)][DBLP]
    PDP, 2004, pp:112-119 [Conf]
  7. Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares
    Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:136-150 [Conf]

  8. Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. [Citation Graph (, )][DBLP]


  9. Improving SMT performance: an application of genetic algorithms to configure resizable caches. [Citation Graph (, )][DBLP]


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