The SCEAS System
Navigation Menu

Search the dblp DataBase


Andrea Marongiu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Giovanni Busonera, Salvatore Carta, Andrea Marongiu, Luigi Raffo
    Automatic Application Partitioning on FPGA/CPU Systems Based on Detailed Low-Level Information. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:265-268 [Conf]
  2. Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
    Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:145-149 [Conf]

  3. Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy. [Citation Graph (, )][DBLP]

  4. Efficient OpenMP data mapping for multicore platforms with vertically stacked memory. [Citation Graph (, )][DBLP]

  5. Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology. [Citation Graph (, )][DBLP]

  6. OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs. [Citation Graph (, )][DBLP]

  7. Scalable instruction set simulator for thousand-core architectures running on GPGPUs. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.002secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002