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John A. Chandy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John A. Chandy, A. L. Narasimha Reddy
    Failure Evaluation of Disk Array Organizations. [Citation Graph (2, 0)][DBLP]
    ICDCS, 1993, pp:319-326 [Conf]
  2. John A. Chandy
    Storage Allocation in Unreliable Peer-to-Peer Systems. [Citation Graph (0, 0)][DBLP]
    DSN, 2006, pp:227-236 [Conf]
  3. Janardhan Singaraju, John A. Chandy
    A Generic Lookup Cache Architecture for Network Processing Applications. [Citation Graph (0, 0)][DBLP]
    ERSA, 2006, pp:247-248 [Conf]
  4. Long Bu, John A. Chandy
    FPGA Based Network Intrusion Detection using Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:316-317 [Conf]
  5. Janardhan Singaraju, Long Bu, John A. Chandy
    A Signature Match Processor Architecture for Network Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:235-242 [Conf]
  6. Janardhan Singaraju, John A. Chandy
    A generic lookup cache architecture for network processing applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:233- [Conf]
  7. Long Bu, John A. Chandy
    A keyword match processor architecture using content addressable memory. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:372-376 [Conf]
  8. John A. Chandy, Prithviraj Banerjee
    A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:621-627 [Conf]
  9. John A. Chandy, Prithviraj Banerjee
    Reliability Evalutaion of Disk Array Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:263-267 [Conf]
  10. Daniel J. Palermo, Ernesto Su, John A. Chandy, Prithviraj Banerjee
    Communication Optimizations Used in the PARADIGM Compiler for Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:1-10 [Conf]
  11. John G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee
    Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:172-179 [Conf]
  12. Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee
    Parallel algorithms for logic synthesis using the MIS approach. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:579-585 [Conf]
  13. SungHo Kim, Prithviraj Banerjee, Balkrishna Ramkumar, Steven Parkes, John A. Chandy
    ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:932-941 [Conf]
  14. Zhaoyun Xing, John A. Chandy, Prithviraj Banerjee
    Parallel Global Routing Algorithms for Standard Cells. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:527-0 [Conf]
  15. John A. Chandy, Steven Parkes, Prithviraj Banerjee
    Distributed Object Oriented Data Structures and Algorithms for VLSI CAD. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1996, pp:147-158 [Conf]
  16. Jonathan D. Bright, John A. Chandy
    A Scalable Architecture for Clustered Network Attached Storage. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Mass Storage Systems, 2003, pp:196-206 [Conf]
  17. Jonathan D. Bright, John A. Chandy
    Data Integrity in a Distributed Storage System. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:688-694 [Conf]
  18. John A. Chandy
    RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:963-969 [Conf]
  19. Michael P. Kapralos, John A. Chandy
    A Quorum Based Content Delivery Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:991-996 [Conf]
  20. Steven Parkes, John A. Chandy, Prithviraj Banerjee
    A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:69-78 [Conf]
  21. John A. Chandy, Prithviraj Banerjee
    Parallel simulated annealing strategies for VLSI cell placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:37-42 [Conf]
  22. Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, Ernesto Su
    The Paradigm Compiler for Distributed-Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:10, pp:37-47 [Journal]
  23. John A. Chandy, Prithviraj Banerjee
    A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:57, n:1, pp:64-90 [Journal]
  24. A. L. Narasimha Reddy, John A. Chandy, Prithviraj Banerjee
    Design and Evaluation of Gracefully Degradable Disk Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:17, n:1-2, pp:28-40 [Journal]
  25. John A. Chandy, Sumit Narayan
    Reliability tradeoffs in personal storage systems. [Citation Graph (0, 0)][DBLP]
    Operating Systems Review, 2007, v:41, n:1, pp:37-41 [Journal]
  26. John A. Chandy, SungHo Kim, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee
    An evaluation of parallel simulated annealing strategies with application to standard cell placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:398-410 [Journal]
  27. Long Bu, John A. Chandy
    A CAM-based keyword match processor architecture. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:8, pp:828-836 [Journal]

  28. Active storage using object-based devices. [Citation Graph (, )][DBLP]


  29. An analysis of resource costs in a public computing grid. [Citation Graph (, )][DBLP]


  30. Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. [Citation Graph (, )][DBLP]


  31. Parity Redundancy Strategies in a Large Scale Distributed Storage System. [Citation Graph (, )][DBLP]


  32. An Analysis of Parallel Programming Techniques for Data Intensive Computation. [Citation Graph (, )][DBLP]


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