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Publications of Author

1. Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
   CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. [Citation Graph (0, 0)][DBLP]
   DSN, 2006, pp:301-312 [Conf]
   
2. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
   Thread-Level Speculation on a CMP can be energy efficient. [Citation Graph (0, 0)][DBLP]
   ICS, 2005, pp:219-228 [Conf]
   
3. Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
   A Model for Timing Errors in Processors with Parameter Variation. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:647-654 [Conf]
   
4. Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
   ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. [Citation Graph (0, 0)][DBLP]
   MICRO, 2005, pp:257-270 [Conf]
   
5. Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
   Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. [Citation Graph (0, 0)][DBLP]
   MICRO, 2006, pp:26-37 [Conf]
   
6. Smruti R. Sarangi, P. N. Sireesh, Sudebkumar Prasant Pal
   A scalable, efficient and general Monte Carlo scheme for generating synthetic web request streams. [Citation Graph (0, 0)][DBLP]
   Comput. Syst. Sci. Eng., 2003, v:18, n:3, pp:121-128 [Journal]
   
7. Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas
   Energy-Efficient Thread-Level Speculation. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2006, v:26, n:1, pp:80-91 [Journal]
   
8. Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas
   ReCycle: : pipeline adaptation to tolerate process variation. [Citation Graph (0, 0)][DBLP]
   ISCA, 2007, pp:323-334 [Conf]
   
9. Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
   Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1261-1264 [Conf]
   
10. Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas
    Patching Processor Design Errors with Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:12-25 [Journal]
    
11. 
    Theoretical Framework for Eliminating Redundancy in Workflows. [Citation Graph (, )][DBLP]
    
    
12. 
    DUST: a generalized notion of similarity between uncertain time series. [Citation Graph (, )][DBLP]
    
    
13. 
    EVAL: Utilizing processors with variation-induced timing errors. [Citation Graph (, )][DBLP]