|
Search the dblp DataBase
Brian Greskamp:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. [Citation Graph (0, 0)][DBLP] DSN, 2006, pp:301-312 [Conf]
- Brian Greskamp, Ron Sass
A Virtual Machine for Merit-Based Runtime Reconfiguration. [Citation Graph (0, 0)][DBLP] FCCM, 2005, pp:287-288 [Conf]
- Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
A Model for Timing Errors in Processors with Parameter Variation. [Citation Graph (0, 0)][DBLP] ISQED, 2007, pp:647-654 [Conf]
- Ron Sass, Brian Greskamp, Brian Leonard, Jeff Young, Srinivas Beeravolu
Online architectures: A theoretical formulation and experimental prototype. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:6, pp:319-333 [Journal]
- Brian Greskamp, Smruti R. Sarangi, Josep Torrellas
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1261-1264 [Conf]
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. [Citation Graph (, )][DBLP]
Blueshift: Designing processors for timing speculation from the ground up. [Citation Graph (, )][DBLP]
The BubbleWrap many-core: popping cores for sequential acceleration. [Citation Graph (, )][DBLP]
EVAL: Utilizing processors with variation-induced timing errors. [Citation Graph (, )][DBLP]
Estimating design time for system circuits. [Citation Graph (, )][DBLP]
Search in 0.001secs, Finished in 0.002secs
|