|
Search the dblp DataBase
Tsukasa Yamauchi:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi
Evolvable Hardware Chip for High Precision Printer Image Compression. [Citation Graph (0, 0)][DBLP] AAAI/IAAI, 1998, pp:486-491 [Conf]
- Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. [Citation Graph (0, 0)][DBLP] FCCM, 2000, pp:281-282 [Conf]
- Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
Arithmetic Operation Oriented Reconfigurable Chip: RHW. [Citation Graph (0, 0)][DBLP] FPL, 2001, pp:618-622 [Conf]
- Tsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine. [Citation Graph (0, 0)][DBLP] ICCAD, 1991, pp:340-343 [Conf]
- Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shougo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. [Citation Graph (0, 0)][DBLP] ICES, 1998, pp:1-12 [Conf]
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. [Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.002secs
|