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Laurent Arditi :
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Laurent Arditi , Hélène Collavizza An Object-Oriented Framework for the Formal Verification of Processors. [Citation Graph (0, 0)][DBLP ] ECOOP, 1995, pp:215-234 [Conf ] Laurent Arditi , Hédi Boufaïed , Arnaud Cavanié , Vincent Stehlé Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System. [Citation Graph (0, 0)][DBLP ] FME, 2001, pp:449-464 [Conf ] Laurent Arditi BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions. [Citation Graph (0, 0)][DBLP ] FMCAD, 1996, pp:34-48 [Conf ] Laurent Arditi , Gérard Berry , Michael Kishinevsky Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs. [Citation Graph (0, 0)][DBLP ] FMCAD, 2004, pp:128-143 [Conf ] Towards verifying VHDL descriptions of processors. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.001secs